3D Die Structure With Embedded IPD for PCB Surface Area Limits
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing integration density and component mounting due to reduced surface area on printed circuit boards (PCBs), necessitating innovative packaging solutions that relocate electrical components from surface areas to within dielectric layers of semiconductor dies.
Innovation Solution
The implementation of three-dimensional device structures that incorporate deep trench capacitors (DTCs) embedded within dielectric layers, allowing for the relocation of integrated passive devices (IPDs) such as capacitors, thereby freeing up surface area for other components and enhancing space utilization efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If electrical components are mounted on surface areas of PCBs, then ease of mounting is improved, but available surface area is reduced as PCBs become smaller
Solution Approach 1:
The patent relocates electrical components from the two-dimensional PCB surface to the three-dimensional space within dielectric layers of semiconductor dies. This dimensional transition allows components to be embedded vertically within the package structure rather than mounted horizontally on the surface, effectively increasing space utilization without compromising mounting capability
Solution Approach 2:
The patent embeds integrated passive devices (IPDs) such as capacitors within the dielectric layers of semiconductor dies, creating a nested structure where components are housed inside the package itself. This nesting approach allows multiple components to coexist in the vertical space, freeing up PCB surface area while maintaining all necessary electrical connections
2Productivity
If minimum feature size is reduced to increase integration density, then component count per area is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by embedding IPDs within dielectric layers. This allows integration density to increase through the third dimension (depth) rather than requiring continuous reduction of minimum feature sizes in the planar direction, thereby relaxing manufacturing precision requirements while still achieving higher component density
3Productivity
If three-dimensional device structures are implemented, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent divides the semiconductor package into distinct functional segments: active components on dies, embedded passive devices within dielectric layers, and interconnect structures. This segmentation allows each component type to be optimized independently and assembled into a three-dimensional configuration, achieving high integration density while managing complexity through modular design
Solution Approach 2:
The dielectric layers serve multiple functions: they provide electrical insulation between conductive layers, mechanical support for embedded IPDs, and structural framework for the three-dimensional package. This multi-functionality reduces the need for additional dedicated structures, thereby increasing integration density without proportionally increasing device complexity
Data Source
AI summary
A three-dimensional device structure includes a first die including a first semiconductor substrate, a second die disposed on the first die and including a second semiconductor substrate, a dielectric encapsulation (DE) layer disposed on the first die and surrounding the second die, a redistribution layer structure disposed on the second die and the DE layer, and an integrated passive device (IPD) embedded in the DE layer and electrically connected to the first die and the redistribution layer structure.