3D Die Package Ground Path Structure for Reliable Integration

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Solution Overview

Problem

Integration of multiple semiconductor devices into a single package has become a challenge in the field of semiconductor manufacturing, particularly in achieving efficient and reliable 3D packaging and 3DIC devices.

Innovation Solution

The solution involves a manufacturing process that includes forming a carrier with semiconductor materials, depositing dielectric and bonding layers, placing and bonding dies with interconnection structures, encapsulating with molding compounds, and forming through insulating vias and bonding vias to establish electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple semiconductor devices are integrated into a single package, then device functionality and performance are improved, but manufacturing complexity increases

Engineering Contradiction:
Improvedevice integration capabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The manufacturing process is divided into distinct stages: forming the semiconductor carrier with first dies, bonding second dies to the first dies, and encapsulating each die separately. This segmentation allows complex multi-die integration to be managed through standardized, repeatable steps, reducing overall manufacturing complexity while maintaining high integration capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a hierarchical packaging structure where second dies are bonded onto first dies, and both are encapsulated within a共同 package structure. This nested arrangement enables multiple devices to be integrated in a compact 3D configuration, achieving high functionality without proportionally increasing manufacturing complexity through modular assembly.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If through insulating vias and bonding vias are formed to establish electrical connections, then electrical connectivity and reliability are improved, but manufacturing steps and time increase

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidmanufacturing cycle time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The semiconductor carrier is pre-formed with contact vias and grounding structures before die bonding. Through insulating vias are formed in the encapsulant prior to final assembly, establishing electrical connection pathways in advance. This preliminary preparation reduces the complexity and time of subsequent bonding operations while ensuring reliable electrical connectivity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Through insulating vias serve as intermediary elements that establish electrical connections between the encapsulant, semiconductor carrier, and dies. These via structures act as mediators that enable reliable electrical connectivity while integrating multiple manufacturing steps into a streamlined process, reducing overall cycle time.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If dies are encapsulated with molding compounds, then device protection and reliability are improved, but manufacturing complexity and material usage increase

Engineering Contradiction:
Improvedevice protectionVSAvoidmolding compound material usage
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

Each die is encapsulated with its own molding compound encapsulant (first encapsulant for first dies, second encapsulant for second dies), providing localized protection tailored to each die's specific requirements. This approach ensures optimal protection for each device while allowing precise control over material usage, avoiding excessive encapsulant application.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12272622B2Package and manufacturing method thereof
Publication Date: 2025.04.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12272622B2 patent drawing
  • US12272622B2 patent drawing
  • US12272622B2 patent drawing

AI summary

A package includes a semiconductor carrier, a first die, a second die, a redistribution structure, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The redistribution structure is over the second die. The electron transmission path extends from the semiconductor carrier to the redistribution structure. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die, and a third portion of the electron transmission path is aside the second die.