3D Die Interconnect Layout for High-Density Low-Latency Bonding
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high connection density and reducing latency and signal integrity issues due to limitations in interconnection methods between semiconductor dies, particularly with the use of bond wires and through-silicon vias, which result in increased IR drop and latency.
Innovation Solution
The implementation of a redistribution structure with interconnect structures that include via structures and lateral conductive elements, allowing connections between adjacent and non-adjacent tiles at distances less than the Manhattan distance, and the use of semiconductor bridges for efficient signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bond wires and through-silicon vias are used for interconnection between semiconductor dies, then device complexity is reduced and ease of manufacture is improved, but connection density is limited and latency increases
Solution Approach 1:
The patent transitions from traditional bond wire and through-silicon via interconnection methods to a three-dimensional integrated circuit architecture with multiple stacked semiconductor dies. This dimensional change enables significantly higher connection density by utilizing vertical stacking and through-die vias, allowing connections to be made in three dimensions rather than confined to a planar two-dimensional layout.
Solution Approach 2:
The patent divides the semiconductor device into multiple separate semiconductor dies that are stacked and interconnected. Each die can be manufactured independently using standard CMOS processes, then bonded together with high-density interconnect structures. This segmentation allows for higher overall connection density while maintaining ease of manufacture through modular assembly.
2Device complexity
If traditional interconnection methods are used, then device complexity is lower, but signal integrity deteriorates due to increased IR drop and latency
Solution Approach 1:
The patent employs three-dimensional stacking with vertical through-die vias to create shorter and more direct signal paths between functional blocks on different dies. This dimensional approach reduces the horizontal distance signals must travel, thereby reducing IR drop and latency while improving signal integrity, despite the increased structural complexity of the stacked architecture.
3Productivity
If connection density is increased using traditional methods, then more connections can be made, but latency and IR drop increase
Solution Approach 1:
The patent achieves high connection density by stacking semiconductor dies vertically and using through-die vias for interconnection. This three-dimensional approach allows numerous connections to be made in a compact volume while maintaining short signal paths, thereby increasing connection density without proportionally increasing latency or IR drop that would occur with traditional planar expansion.
Data Source
AI summary
A semiconductor device includes a plurality of top semiconductor dies. Each of the plurality of top semiconductor dies can be bonded to a bottom semiconductor die. The semiconductor device includes a redistribution structure disposed opposite the plurality of top semiconductor dies from the plurality of bottom semiconductor dies and comprising a plurality of interconnect structures. A top semiconductor die can connect to another top semiconductor die via a first subset of the plurality of interconnect structures.