3D Die Array Packaging With Hybrid Bonding for High I/O Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor technologies advance, integrated circuit dies become smaller with increased functions, leading to a higher density of input/output (I/O) pads, which complicates packaging due to reduced available area, necessitating innovative packaging solutions to enhance parallel processing capabilities.
Innovation Solution
The formation of a system-on-integrated-chip (SoIC) device by stacking die arrays in a checkerboard pattern, allowing for a three-dimensional die network with logic and memory dies intermingled, utilizing hybrid bonding for electrical connections without solder, to increase packing density and improve memory access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integrated circuit dies are made smaller with increased functions, then the number of I/O pads needed increases, but the area available for I/O pads decreases
Solution Approach 1:
The patent transitions from two-dimensional planar packaging to three-dimensional stacked packaging. Multiple dies are vertically stacked and interconnected, allowing I/O pads to be distributed across multiple layers and surfaces. This dimensional change enables significantly more I/O pads to be accommodated within a reduced footprint area by utilizing the vertical dimension for additional connection points and redistribution.
2Productivity
If multiple dies are integrated to increase parallel processing capabilities, then computing efficiency improves, but packaging complexity increases
Solution Approach 1:
The system is divided into multiple discrete dies that can be independently manufactured, tested, and then stacked. Each die is a separate functional unit that can be optimized independently. This segmentation allows for modular assembly and simplifies the packaging process by breaking down the complex multi-die integration into manageable stages of individual die preparation and subsequent stacking.
Solution Approach 2:
Multiple dies are nested vertically in a stacked configuration, with each die containing functional elements that interconnect with adjacent dies. This nesting approach consolidates multiple processing units into a compact vertical structure, increasing parallel processing capability while managing packaging complexity through hierarchical organization of die layers and their interconnections.
Data Source
AI summary
In an embodiment, a device includes: a first die array including first integrated circuit dies, orientations of the first integrated circuit dies alternating along rows and columns of the first die array; a first dielectric layer surrounding the first integrated circuit dies, surfaces of the first dielectric layer and the first integrated circuit dies being planar; a second die array including second integrated circuit dies on the first dielectric layer and the first integrated circuit dies, orientations of the second integrated circuit dies alternating along rows and columns of the second die array, front sides of the second integrated circuit dies being bonded to front sides of the first integrated circuit dies by metal-to-metal bonds and by dielectric-to-dielectric bonds; and a second dielectric layer surrounding the second integrated circuit dies, surfaces of the second dielectric layer and the second integrated circuit dies being planar.