3D Die Stack Interconnect for Source-Synchronous Data Transfer
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Solution Overview
Problem
In 3D die stacks, synchronous data transfer between dies with different process technologies often experiences timing drift and latency due to separate reference clock sources, leading to increased latency and reduced throughput, especially when setup and hold periods are required.
Innovation Solution
Implementing source-synchronous data transfer with the clock signal co-located among data signals over microbump connections, ensuring both signals experience similar propagation delays, eliminating the need for setup and hold times and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate reference clock sources are used for each die in a 3D die stack, then each die can operate independently with its own process technology, but timing drift and latency occur between dies
Solution Approach 1:
The patent merges the clock and data signals into a single source-synchronous interface. The clock signal is distributed through the same interconnect medium (microbumps) as the data signals, ensuring both signals experience identical propagation delays. This eliminates timing drift between separate clock and data paths while maintaining compatibility across different process technologies through the HBI interconnect.
2Adaptability or versatility
If synchronous data transfer with separate clock sources is used, then dies with different process technologies can be bonded together, but setup and hold periods are required increasing latency
Solution Approach 1:
The source-synchronous interface allows the data signal itself to carry timing information from its source. Each die generates and transmits its own clock signal through the same microbump interconnect as its data signals, making the system self-synchronized without requiring external clock distribution or setup/hold periods. This eliminates the productivity penalty of synchronous transfer while maintaining the versatility of bonding different process technologies.
3Device complexity
If clock and data signals are transmitted separately over the interconnect, then signal routing is simplified, but propagation delay differences cause timing drift
Solution Approach 1:
The patent combines clock and data signals into a unified source-synchronous transmission scheme. Both signals traverse the same physical path through the microbump interconnect, ensuring identical propagation delays. This merging approach actually simplifies the overall system by eliminating the need for separate clock distribution networks and complex timing synchronization logic, while simultaneously eliminating propagation delay variations.
Data Source
AI summary
An example integrated circuit disclosed herein includes a first die including first microbumps associated with a source-synchronous data interface of a three-dimensional (3D) die stack, a first one of the first microbumps in circuit with a clock output of the first die, a second one of the first microbumps in circuit with a data output of the first die, the clock output and the data output associated with a transmitter side of the source-synchronous data interface. The example integrated circuit also includes a second die including second microbumps associated with the source-synchronous data interface of the 3D die stack, a first one of the second microbumps in circuit with a clock input of the second die, a second one of the second microbumps in circuit with a data input of the second die, the clock input and the data input associated with a receiver side of the source-synchronous data interface.