3D Die Stack Interconnect for Source-Synchronous Data Transfer
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Solution Overview
Problem
Existing data transfer techniques between dies in a 3D die stack, particularly those with different process technologies, suffer from timing drift and latency, leading to increased latency and reduced throughput due to the use of synchronous data transfer methods that require setup and hold periods.
Innovation Solution
Implementing source-synchronous data transfer with co-located clock and data connections between dies, where the transmitter generates and synchronizes the clock with the data, reducing timing drift and eliminating the need for setup and hold times by ensuring similar propagation delays for both signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous data transfer methods are used between dies with different process technologies, then data transfer can be performed, but timing drift and latency occur due to setup and hold periods
Solution Approach 1:
The patent merges the clock signal and data signals into a single differential pair, eliminating the separate clock connection. The transmitter generates both clock and data on the same signal path, ensuring identical propagation delays and removing the need for separate timing synchronization, thereby eliminating setup and hold time requirements.
Solution Approach 2:
The patent uses differential signaling where the clock and data are represented as differential voltage transitions. The receiver detects these differential transitions to recover timing information, effectively copying the timing reference within the data signal itself, which eliminates the need for separate clock distribution and associated timing drift.
2Ease of operation
If separate clock and data connections are used, then synchronous data transfer is possible, but propagation delay differences cause timing drift
Solution Approach 1:
The patent combines clock and data into a single differential signal path. The transmitter modulates both clock and data information onto the same physical connection, ensuring that both signals experience identical propagation delays through the interconnect, thereby eliminating timing drift caused by separate path variations.
3Reliability
If setup and hold periods are implemented, then data sampling reliability is improved, but data throughput is reduced
Solution Approach 1:
The patent embeds the clock timing reference within the data signal itself using differential transitions. The receiver detects the differential transitions to automatically recover timing information, eliminating the need for separate setup and hold periods while maintaining sampling reliability, thereby maximizing data throughput.
Data Source
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AI summary
An example integrated circuit (100) disclosed herein includes a first die (105) including first microbumps (135) associated with a source-synchronous data interface of a three-dimensional, 3D, die stack, a first one of the first microbumps in circuit with a clock output (125) of the first die, a second one of the first microbumps in circuit with a data output (130) of the first die, the clock output and the data output associated with a transmitter side of the source-synchronous data interface. The example integrated circuit also includes a second die (110) including second microbumps (150) associated with the source-synchronous data interface of the 3D die stack, a first one of the second microbumps in circuit with a clock input of the second die, a second one of the second microbumps in circuit with a data input of the second die, the clock input and the data input associated with a receiver side of the source-synchronous data interface.