3D Die Stack Redistribution Layer for Backside Power Delivery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current package architectures for integrated circuit devices face challenges in meeting the increasing power and compute bandwidth demands of CPUs and GPUs, particularly in providing efficient power delivery and input/output routing, which limits performance and efficiency.
Innovation Solution
A multichip composite architecture is introduced, featuring a topside metallization network that routes power directly to the backside of integrated circuit dies, utilizing a thick metal redistribution layer on top of compute dies, which includes a disaggregated voltage regulator to improve power delivery and reduce routing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If current package architectures are used for power delivery, then existing routing structures are maintained, but power efficiency deteriorates and IR drop increases under high power demands
Solution Approach 1:
The patent introduces a third-dimensional vertical power delivery pathway by stacking multiple die layers with metallization networks on each layer. Power is delivered vertically through through-silicon vias (TSVs) and backside metallization, transitioning from traditional planar 2D routing to 3D vertical routing, which reduces current path length and associated IR drops
Solution Approach 2:
The power delivery network is segmented into multiple functional layers: frontside metallization for signal routing, backside metallization for power distribution, and intermediate redistribution layers. This segmentation allows optimized power pathways separate from signal routing, improving power efficiency and reducing interference
2Area of stationary object
If traditional routing structures are used, then existing die layouts are maintained, but compute area is reduced due to routing restrictions
Solution Approach 1:
By implementing backside metallization and vertical through-silicon via connections, the patent moves power and ground routing to the third dimension, freeing up the frontside die surface from extensive power routing traces. This allows significantly more compute area on the frontside while maintaining power delivery capability through vertical pathways
Solution Approach 2:
The power delivery function is extracted from the frontside metallization network and relocated to dedicated backside metallization layers. This separation removes routing restrictions from the compute area, allowing uninterrupted frontside layout optimization for computational elements
3Use of energy by moving object
If power delivery is improved through enhanced routing, then power efficiency increases, but device complexity increases
Solution Approach 1:
The backside metallization network serves multiple functions simultaneously: power distribution, ground return paths, and thermal management. The through-silicon vias serve dual purposes as both electrical interconnects and structural alignment features. This multi-functionality reduces the need for separate dedicated structures, managing complexity while achieving superior power delivery
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
Microelectronic devices, assemblies, and systems include a multichip architecture having one or more integrated circuit dies over and bonded to a base die, and a metallization network over the integrated circuit die(s). A backside metallization of the integrated circuit die(s) is proximal to the metallization network and a frontside metallization of the integrated circuit die(s) is opposite a device layer from the backside metallization. A via lateral to the base die couples to the metallization network to provide an electrical routing to the backside metallization of the integrated circuit die(s) through the via and the metallization network.