3D Die Test Control Port for Independent Stack Testing
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Solution Overview
Problem
In 3D die stacks, testing each die individually after stacking is necessary to ensure only known good dies are used, and the interconnects between dies need to be tested for integrity, which is inefficient and requires a common test architecture across all dies.
Innovation Solution
A common test architecture is implemented in each die of a 3D die stack, utilizing parallel scan techniques to access and test digital circuits within each die, allowing for independent testing regardless of the die's location in the stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual testing is performed on each die after stacking, then the reliability of each die and interconnect is ensured, but the testing time and process complexity increase significantly
Solution Approach 1:
The testing process is segmented into wafer-level testing before stacking and post-stack testing, allowing parallel scan paths to be established independently in each die. This segmentation enables efficient testing by dividing the overall testing task into manageable segments that can be performed at different stages
Solution Approach 2:
Wafer-level testing is performed as a preliminary action before the stacking process, allowing defects to be identified and eliminated early. This preliminary testing reduces the burden on post-stack testing and ensures only known good dies are stacked together
2Ease of operation
If a common test architecture is implemented in each die, then the ease of operation and testing efficiency improve, but the device complexity increases
Solution Approach 1:
A universal test architecture is implemented in each die that can perform multiple testing functions including parallel scan path establishment, interconnect testing, and die integrity verification. This multi-functional architecture improves ease of operation by providing consistent testing capabilities across all dies while managing complexity through standardized designs
Solution Approach 2:
The test architecture utilizes controllable parameters such as scan path selection, test mode configuration, and signal routing to achieve different testing objectives. By changing these parameters, the same hardware architecture can perform various testing functions without requiring additional complex circuitry
3Productivity
If parallel scan techniques are used to access digital circuits, then the productivity and testing speed improve, but the device complexity increases
Solution Approach 1:
The patent transitions from traditional serial scanning to parallel scanning by adding a spatial dimension to the test data flow. Multiple scan paths operate simultaneously in parallel, dramatically increasing testing throughput. This dimensional change from serial to parallel architecture is achieved through carefully designed scan path routing and control logic
Data Source
AI summary
A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.