3D Die Stack Through-Via Layout for Flatness and Delamination
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Solution Overview
Problem
Current 3D semiconductor package structures face issues with low flatness of through-silicon via (TSV) structures due to over-grinding and thermal expansion, leading to performance degradation and increased size.
Innovation Solution
Incorporating interlayer dielectric layers and conductive through vias that penetrate multiple layers to electrically connect dies, reducing the need for additional interconnecting structures and minimizing flatness issues during planarization and thermal treatment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TSV structures with interconnecting structures are used in each layer, then electrical connection between dies is achieved, but the flatness of the structure deteriorates and overall size increases
Solution Approach 1:
The patent segments the electrical connection function by implementing conductive through vias that penetrate multiple die layers simultaneously, rather than using separate interconnecting structures between each adjacent die layer. This segmentation approach reduces the total number of connection points and improves flatness while maintaining electrical connectivity.
Solution Approach 2:
The patent transitions from a layer-by-layer interconnection approach to a through-penetrating via approach, effectively changing the dimensional strategy from horizontal interconnecting structures between layers to vertical through-vias spanning multiple layers. This dimensional change reduces the overall structure size and improves flatness.
2Manufacturing precision
If over-grinding is performed during planarization, then surface flatness is improved, but thermal expansion causes delamination and flatness degradation
Solution Approach 1:
The patent applies preliminary anti-action by designing conductive through vias that span multiple layers in a way that pre-compensates for thermal expansion forces. The through-via structure distributes thermal stress across multiple interfaces, preventing delamination before it occurs during thermal processing.
Solution Approach 2:
The patent employs composite material structures in the conductive through vias, combining different materials with complementary properties. This composite approach provides both the electrical conductivity needed for connection and the thermal stability required to resist expansion and delamination during processing.
3Reliability
If interconnecting structures are added between adjacent dies, then electrical conduction is achieved, but device complexity and overall size increase
Solution Approach 1:
The patent merges the electrical connection function across multiple die layers by implementing conductive through vias that penetrate through several layers simultaneously. This consolidates multiple separate interconnecting structures into a single integrated via system, reducing device complexity while maintaining electrical conduction.
Solution Approach 2:
The conductive through vias serve multiple functions simultaneously: they provide electrical connection, maintain structural integrity, and reduce overall device complexity. This multi-functionality eliminates the need for separate dedicated interconnecting structures, simplifying the overall device architecture.
Data Source
AI summary
The present disclosure relates to the technical field of semiconductor manufacturing, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a plurality of dies, where the plurality of dies are stacked layer by layer; one or more interlayer dielectric layers, where each of the interlayer dielectric layers is located between adjacent dies; and a plurality of conductive through vias, where at least one of the plurality of conductive through vias penetrates at least two layers of dies and electrically connects the at least two layers of dies.