3D Die Stacking With Hybrid Bonding for Flatness and Alignment
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Solution Overview
Problem
Existing semiconductor manufacturing methods face challenges in achieving precise alignment and flatness for hybrid bonding in staggered 3-D die stacking due to variations in die thickness, leading to poor contact and bonding quality, which compromises performance and reliability.
Innovation Solution
The use of hybrid bonding techniques with electrical and mechanical connections, combined with supporting structures and encapsulating materials, to achieve nanometer-scale flatness and precise alignment, including the use of through-silicon vias and thru-encapsulation-vias for high-density interconnects, and the incorporation of dummy dies for mechanical robustness and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If hybrid bonding techniques are used to achieve high interconnect density, then electrical performance and component density are improved, but variations in die thickness cause poor contact and bonding quality
Solution Approach 1:
A planarization layer comprising dielectric material is introduced as an intermediary between the semiconductor dies and the bonding interface. This layer fills gaps and compensates for thickness variations in the dies, providing a substantially planar bonding surface that ensures reliable hybrid bonding contact while maintaining the high interconnect density requirements
2Manufacturing precision
If FOWLP molding technique is used to achieve flatness, then coplanarity between dies is improved, but die shift occurs due to uncontrolled mold flow
Solution Approach 1:
The patent applies planarization processing to the encapsulated structure before subsequent bonding operations. By pre-flattening the die surfaces through CMP or similar planarization techniques, the method ensures both coplanarity and precise alignment are achieved before hybrid bonding, eliminating the die shift problem associated with post-encapsulation molding approaches
3Measurement precision
If nanometer-scale flatness is required for hybrid bonding, then bonding precision is improved, but existing methods cannot achieve this level of flatness due to die thickness variations
Solution Approach 1:
The planarization layer serves as a mediator that decouples the die thickness variations from the bonding interface requirements. By introducing this intermediate dielectric layer and applying planarization processing, the system achieves nanometer-scale flatness at the bonding interface without requiring the semiconductor dies themselves to be manufactured with extreme precision, thus maintaining ease of manufacture while achieving high bonding precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of complex, high-density 3-D stacked semiconductor assemblies with enhanced mechanical integrity and electrical performance, supporting advanced computing and telecommunications applications.
Implementation Method 1
a direct bond between the dielectric material (oxide or nitride) is formed
Implementation Method 2
Subsequent heating closes the dishing gap due to the coefficient of thermal expansion (CTE) of metal compared to silicon oxide or nitride
Implementation Method 3
Finally, further heating compresses the metal, e.g., hybrid bonding pads, without external pressure such as to achieve a permanent bond
Data Source
AI summary
Systems and methods are provided for three-dimensional (3-D) stacking of semiconductor dies in a face-to-back staggered pattern, enabling high-density integration and improved electrical performance in semiconductor assemblies. In one example, hybrid bonding techniques, which incorporate both electrical and mechanical connections, are employed to reliably bond semiconductor die in multiple layers with precise alignment.