3D Die Stacking Interposer Buffers for Signal Integrity

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Solution Overview

Problem

Integrated circuit manufacturing processes impose limitations on die size and yield, making it challenging to design larger circuits that require high-speed, high-bandwidth communication between multiple dice, which can lead to signal integrity issues due to added parasitic inductance, capacitance, and resistance.

Innovation Solution

The use of an interposer array connecting multiple logic dice, where each interposer die includes input and output contacts, allowing for high-speed communication between logic dice while minimizing signal degradation by using buffers and active components to amplify signals, and allowing for flexible layout and technology node compatibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the circuit is split into multiple dice, then the die size can be reduced to comply with manufacturing limitations, but the signal integrity deteriorates due to added parasitic inductance, capacitance, and resistance in inter-die communication

Engineering Contradiction:
Improvedie size complianceVSAvoidsignal integrity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

An interposer die is introduced as an intermediary component between multiple logic dice. The interposer provides a centralized location for signal routing and buffering, reducing the parasitic effects of direct inter-die communication while maintaining manufacturing compliance. The interposer's buffers amplify signals and reduce degradation, solving the signal integrity issue that arises from splitting circuits into multiple smaller dice.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If the die size is increased to accommodate larger circuits, then the circuit complexity can be increased, but the manufacturing yield decreases due to higher probability of defects

Engineering Contradiction:
Improvecircuit complexityVSAvoidmanufacturing yield
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The circuit is segmented into multiple smaller logic dice that can be manufactured with high yield, then combined through an interposer. This segmentation allows each individual die to remain within acceptable size limits for manufacturing while achieving the overall circuit complexity needed. The interposer acts as a bridge that connects these smaller, high-yield dice to create a functionally equivalent large circuit.

Inventive Principle:
Principle #1Segmentation

3Reliability

If buffers and active components are added to amplify signals between dice, then signal integrity is improved, but the device complexity increases

Engineering Contradiction:
Improvesignal integrityVSAvoidinterposer complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple buffering and signal conditioning functions are merged into a single interposer die. Rather than adding separate buffer components between each pair of logic dice, the interposer consolidates all signal routing, buffering, and amplification functions in one centralized location. This merging approach improves signal integrity across all inter-die connections while minimizing the overall device complexity compared to distributed buffering solutions.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11942409B2High density low power interconnect using 3D die stacking
Publication Date: 2024.03.26 MARVELL ASIA PTE LTD
  • US11942409B2 patent drawing
  • US11942409B2 patent drawing
  • US11942409B2 patent drawing

AI summary

An integrated circuit includes a first set of dies, each die comprising circuitry and a second set of interposer dies. At least two dies of the first set of dies are connected to each other via at least one of the interposer dies. The at least one of the interposer dies includes first connections connected to a first die of the first set of dies, second connections connected to a second die of the first set of dies, and buffers connected between the first connections and the second connections. The buffers are configured to condition signals between the first die and the second die.