3D Die Stacking With TSV Bonding for Higher Integration Density
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Solution Overview
Problem
The semiconductor industry faces limitations in increasing integration density due to the growing number and length of interconnections between semiconductor devices, which restricts further miniaturization and efficiency in 2D integrated circuit formation.
Innovation Solution
The solution involves a method of forming a die stack with semiconductor dies vertically stacked and bonded using through semiconductor vias (TSVs) and bonding conductors, with a dielectric layer covering the bonding conductors, allowing for efficient electrical connections and increased density without the constraints of 2D layouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D integrated circuit formation is used to increase integration density, then more components can be integrated into a given area, but the number and length of interconnections between semiconductor devices increases significantly
Solution Approach 1:
The patent transitions from traditional 2D integrated circuit layout to 3D stacked architecture by vertically stacking multiple semiconductor dies. This dimensional change allows components to be arranged in three-dimensional space rather than confined to a two-dimensional plane, thereby increasing integration density without proportionally increasing interconnection complexity. The vertical stacking enables shorter interconnect paths through through-silicon vias (TSVs) compared to lateral routing in 2D layouts.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but physical limitations are reached
Solution Approach 1:
Instead of continuously reducing minimum feature size in 2D, the patent exploits the third dimension by stacking semiconductor dies vertically. This approach bypasses the physical limitations of feature size reduction by integrating more components through increased vertical height rather than decreased lateral dimensions, thereby maintaining manufacturability while achieving higher integration density.
3Quantity of substance
If pitch for conductive wirings is decreased to increase integration density, then more components can be integrated, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent replaces lateral wiring routing with vertical interconnections through TSVs in the stacked architecture. This dimensional transition allows for larger effective pitch in the lateral plane while achieving high density through vertical stacking, thereby simplifying manufacturing compared to decreasing wiring pitch in 2D layouts.
Solution Approach 2:
The patent divides the integrated circuit into multiple separate semiconductor dies that are stacked and interconnected. Each die can be manufactured independently with standard pitch requirements, avoiding the need to manufacture entire high-density interconnection networks in a single 2D layer. This segmentation enables conventional manufacturing processes to be used while achieving high overall integration density.
Data Source
AI summary
A manufacturing method of a semiconductor structure is provided. A first semiconductor die includes a first semiconductor substrate, a first interconnect structure formed thereon, a first bonding conductor formed thereon, and a conductive via extending from the first interconnect structure toward a back surface of the first semiconductor substrate. The first semiconductor substrate is thinned to accessibly expose the conductive via to form a through semiconductor via (TSV). A second semiconductor die is bonded to the first semiconductor die. The second semiconductor die includes a second semiconductor substrate including an active surface facing the back surface of the first semiconductor substrate, a second interconnect structure between the second and the first semiconductor substrates, and a second bonding conductor between the second interconnect structure and the first semiconductor substrate and bonded to the TSV. The second bonding conductor is substantially aligned with the first bonding conductor and smaller than the TSV.