3D Die Stacking With Via-First Hybrid Bonding and Vertical TDVs
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Solution Overview
Problem
Current 3D die stacking technologies face challenges in forming high aspect ratio vias through dielectric layers due to the use of inorganic dielectric materials and damascene processes, which are costly and difficult to scale for higher data transfer rates.
Innovation Solution
Employing organic dielectric materials like epoxy mold compounds and a via-first process to form vias before dielectric layer deposition, enabling high aspect ratio and tighter pitch vias with vertical sidewalls, reducing the need for expensive CVD processes and complex patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inorganic dielectric materials are used with CVD/PECVD processes, then dielectric layer deposition is achieved, but via formation becomes difficult due to high aspect ratio requirements and increased manufacturing complexity
Solution Approach 1:
The patent applies preliminary action by forming vias through the dielectric layer before depositing the dielectric material. This reverse sequence allows vias to be created in a planar substrate where access is easier, then the dielectric is deposited over the vias to complete the 3D structure. This eliminates the difficulty of forming high aspect ratio vias through already-deposited thick dielectric layers.
Solution Approach 2:
The patent inverts the conventional manufacturing sequence by depositing dielectric material after via formation rather than before. This inversion transforms an intractable problem (forming vias through thick dielectric) into a solvable one (forming vias in planar substrate, then covering with dielectric).
2Length of stationary object
If dielectric layer thickness is increased to cover upper dies, then complete die coverage is achieved, but via aspect ratio increases making plating and patterning more difficult
Solution Approach 1:
By forming vias before dielectric deposition, the patent ensures that via patterning occurs on a planar surface where precise control is easier. The subsequent dielectric deposition uniformly covers the vias without requiring complex high aspect ratio via formation, thereby maintaining manufacturing precision while achieving the required dielectric thickness.
3Productivity
If interconnect pitch is decreased to accommodate higher data transfer rates, then data transmission capacity increases, but via formation difficulty increases due to tighter spacing requirements
Solution Approach 1:
The patent forms vias with tighter pitch in the planar substrate stage before dielectric deposition, where precise patterning is more controllable. This preliminary via formation at reduced pitch enables higher interconnect density and data transfer rates without the compounding difficulty of simultaneously achieving tight pitch and high aspect ratio in conventional approaches.
4Reliability
If conventional damascene processes are used for via formation, then via structure is achieved, but manufacturing cost increases
Solution Approach 1:
By inverting the manufacturing sequence to form vias before dielectric deposition, the patent eliminates the need for complex damascene processes. The simplified via formation method used in the planar substrate stage reduces manufacturing steps and costs while maintaining via structure integrity through the subsequent dielectric coverage.
Data Source
AI summary
Embodiments disclosed herein comprise a first die with a conductive pad; and a second die over the first die, where the second die has a conductive pad. In an embodiment, the conductive pad of the first die is in direct contact with the conductive pad of the second die. In an embodiment, a layer is above the first die, and the second die is embedded in the layer. In an embodiment, the layer comprises an organic dielectric material. In an embodiment, a via is through the layer, and the via is electrically coupled to the first die. In an embodiment, the via comprises substantially vertical sidewalls.