3D Transistor Dielectric Liners for High-Voltage Gate Isolation
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Solution Overview
Problem
The scaling of multi-gate transistors in semiconductor devices leads to challenges in maintaining high voltage reliability due to reduced spacing between the gate and source/drain contacts, resulting in premature device failure.
Innovation Solution
The implementation of an inside spacer dielectric liner process, which involves the deposition of multiple dielectric layers to provide additional spacing between the gate and source/drain contacts, thereby enhancing the dielectric margin for high voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are scaled to smaller dimensions to increase device density, then the number of functional units per chip area increases, but the spacing between gate and source/drain contacts decreases leading to reduced high voltage reliability
Solution Approach 1:
The patent introduces a vertical dielectric liner structure that extends into the trench contact region, adding a third-dimensional solution to the two-dimensional spacing problem. This vertical extension of the dielectric liner into the contact trench provides additional insulation without affecting the horizontal feature dimensions, thereby maintaining device density while improving high voltage reliability through increased effective spacing between gate and contact regions
Solution Approach 2:
The patent employs a dielectric liner as an intermediary material positioned between the gate structure and the source/drain contacts. This dielectric liner acts as a mediator that provides electrical isolation and prevents premature breakdown, allowing the transistor to maintain high voltage reliability even when scaled to smaller dimensions with reduced spacing
2Productivity
If the spacing between gate and source/drain contacts is reduced to increase device density, then more devices can be fabricated per region, but premature device failure occurs due to insufficient dielectric margin
Solution Approach 1:
The patent applies the dielectric liner formation process early in the fabrication sequence, before trench contact formation and gate patterning. This preliminary action ensures that the dielectric liner is already in place to define the final contact spacing and provide the necessary dielectric margin, preventing premature failure modes from the outset rather than attempting to correct spacing issues later in the process
3Ease of manufacture
If conventional tri-gate fabrication processes are used on bulk silicon substrates to reduce cost and complexity, then manufacturing becomes less complicated, but high voltage reliability is compromised due to insufficient gate-to-contact spacing
Solution Approach 1:
The patent applies the dielectric liner specifically in the trench contact regions adjacent to the gate, rather than uniformly throughout the entire device structure. This localized application provides the necessary high voltage isolation where it is most critical (at the gate-to-contact interfaces) while maintaining the simplicity of conventional bulk silicon tri-gate fabrication processes in other regions of the device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable high-voltage operation by increasing the gate-to-contact spacing, thereby reducing the risk of premature device failure and improving the overall reliability of the transistors.
Implementation Method 1
the deposition of multiple dielectric layers to provide additional spacing between the gate and source/drain contacts
Data Source
AI summary
High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.