3D DMA Configuration for Faster Radar Baseband Detection

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Solution Overview

Problem

Conventional radar systems, particularly in automotive applications, suffer from slow software-based processing speeds in baseband processors, which hinder efficient object detection and velocity determination.

Innovation Solution

Implementing a Direct Memory Access (DMA) circuit and detection circuit in conjunction with fast Fourier transform (FFT) circuits to streamline processing, reducing software overhead and enhancing the speed of object detection in radar systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If software-based processing is used in baseband processors, then flexibility is maintained, but processing speed becomes slow

Engineering Contradiction:

Improveprocessing speedVSAvoidsoftware overhead

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent replaces software-based processing with hardware-based processing using FFT circuits and DMA controllers. The FFT circuits perform fast Fourier transforms in hardware, and the DMA controller automatically transfers data between memory and processing units without software intervention, eliminating software overhead and significantly improving processing speed.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The DMA controller operates autonomously to manage data transfer between memory and processing circuits. It automatically generates memory access patterns, transfers data without CPU intervention, and manages the radar data cube processing workflow independently, reducing the burden on the baseband processor and improving overall system efficiency.

Inventive Principle:

Principle #25Self-service

2Reliability

If complete radar data cube is stored in memory, then all data is available for processing, but memory requirements and processing time increase

Engineering Contradiction:

Improvedata availabilityVSAvoidprocessing time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts and processes only the necessary portions of the radar data cube using DMA-configured memory access patterns. Instead of loading and processing the complete data cube, the system selectively accesses specific range-Doppler cells that contain target information, reducing memory requirements and processing time while maintaining detection reliability.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The radar data cube is segmented into multiple range-Doppler cells, and the DMA controller processes these segments in parallel or sequential batches. This segmentation allows the system to process data in manageable chunks rather than requiring all data to be loaded simultaneously into memory, improving both speed and memory efficiency.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12584996B2Hardware generation of 3D DMA configurations

Publication Date: 2026.03.24 INFINEON TECHNOLOGIES AG

AI summary

A baseband processor including a fast Fourier transform (FFT) circuit having an FFT input and an FFT output. A first processing path having a first processing path input and a first processing path output. The first processing path including a memory coupled to the FFT output and the first processing path input via a first bus. A Direct Memory Access (DMA) coupled between the memory and the first processing path output. The DMA coupled to the memory via a second bus. A second processing path arranged in parallel with the first processing path. The second processing path including a detection circuit having a detection circuit input coupled to the FFT output and having a detection circuit output coupled to the DMA.