3D DRAM Ancillary Electrode for Bit Line Impedance Control
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Solution Overview
Problem
Conventional three-dimensional DRAM bit lines formed via ion-doping exhibit high impedance, leading to signal transmission losses and reduced charge storage in capacitors.
Innovation Solution
A three-dimensional DRAM structure incorporating an ancillary electrode structure, which includes a substrate, bit lines formed by doping and diffusion, pillar elements, dielectric layers, and character lines, where the ancillary electrode is strategically positioned to control bit line impedance and enhance conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bit lines are formed via ion-doping method, then fabrication process is simplified and couple noise is reduced, but impedance of bit lines becomes much greater leading to signal transmission loss
Solution Approach 1:
An ancillary electrode structure is introduced as an intermediary element between the ion-doped bit line and the capacitor. This ancillary electrode serves as a mediator that compensates for the high impedance of the ion-doped bit line, enabling effective signal transmission while preserving the fabrication simplicity of the ion-doping method.
Solution Approach 2:
The invention changes the electrical parameters of the bit line system by introducing the ancillary electrode with specific electrical characteristics. This alters the overall impedance profile and electrical behavior of the bit line, transforming it from a high-impedance structure unsuitable for signal transmission to a low-impedance structure that maintains signal integrity.
2Ease of manufacture
If bit lines are formed via ion-doping method, then fabrication process is simplified, but conductivity of bit lines decreases resulting in charge loss in capacitor
Solution Approach 1:
The ancillary electrode acts as an intermediary that bridges the high-impedance ion-doped bit line and the capacitor. This mediator reduces the overall impedance path, enabling more efficient charge transfer and reducing energy loss during charging and discharging operations.
Solution Approach 2:
The invention introduces a three-dimensional ancillary electrode structure that adds a vertical dimension to the bit line configuration. This dimensional change creates additional conductive pathways and reduces the effective resistance, thereby minimizing charge loss while maintaining the simple ion-doping fabrication process.
3Area of stationary object
If vertical pillar transistor structure is adopted, then wafer occupied area is reduced, but bit line impedance control becomes challenging
Solution Approach 1:
The ancillary electrode structure utilizes the vertical dimension to provide impedance control functionality without increasing the lateral footprint. By extending the bit line structure into the third dimension, the invention achieves effective impedance management while maintaining the compact area characteristics of vertical pillar transistor architectures.
Solution Approach 2:
The ancillary electrode is nested within or adjacent to the existing vertical pillar transistor structure, sharing the same vertical space. This nesting approach allows impedance control functionality to be integrated without increasing the overall device footprint, maintaining area efficiency while improving electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ancillary electrode structure significantly reduces bit line impedance, improving conductivity and stability, and maintains fabrication compatibility with existing vertical pillar transistor processes, resulting in enhanced performance and yield.
Implementation Method 1
The bit line is formed on the substrate by doping and diffusing a doping element
Data Source
AI summary
A three-dimensional dynamic random access memory with an ancillary electrode structure includes a substrate, at least one bit line formed on the substrate, at least one pillar element formed on a growth zone of the bit line, an ancillary electrode, a character line parallel with the substrate and perpendicular to the bit line, and at least one capacitor connecting to the pillar element. The bit line is formed on the substrate by doping and diffusing a doping element. The ancillary electrode is located on a separation zone of the bit line and adjacent to the pillar element. The character line is insulated from the ancillary electrode and incorporates with the bit line to output or input electronic data to the capacitor. Through the ancillary electrode, impedance of the bit line can be controlled to enhance conductivity of the bit line.