3D Stacked DRAM Vertical Bank Redundancy for Yield Repair
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Solution Overview
Problem
Conventional 3D stacked DRAM yield is limited due to low-cost wafer-to-wafer stacking, and existing repair techniques fail to increase single DRAM wafer yield to desired levels, while bank-level redundancy is impractical due to area penalties.
Innovation Solution
Implementing vertical bank redundancy in 3D stacked DRAM with a repair circuit that remaps addresses across different memory dies, allowing both row-block redundancy within a bank tile and across 3D vertical stacks, using shared data TSVs and tri-state switches for efficient bank replacement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional repair techniques (redundant row, column, and ECC) are used, then some defect coverage is achieved, but single DRAM wafer yield cannot reach desired levels
Solution Approach 1:
The patent transitions from conventional 2D repair techniques to 3D vertical bank redundancy across stacked memory dies. By stacking multiple memory dies and implementing bank-level redundancy in the vertical dimension, the system achieves superior defect coverage and yield improvement that cannot be obtained through traditional planar repair methods alone.
Solution Approach 2:
The patent divides the memory system into multiple stacked dies with independent bank structures. Each die can be independently repaired or replaced, and the vertical stacking allows selective activation of redundant banks across different dies, enabling more granular and effective defect management.
2Productivity
If bank-level redundancy is implemented in 3D stacked memories, then yield is improved, but area penalty increases
Solution Approach 1:
Instead of adding redundant banks in the horizontal plane which consumes area, the patent utilizes the vertical dimension by stacking multiple memory dies. The redundant banks are distributed across different stacked dies, achieving bank-level redundancy without increasing the footprint area of individual dies.
Solution Approach 2:
The patent merges multiple memory dies into a single 3D stacked structure where redundant banks from different dies work together. This consolidation allows the system to achieve comprehensive bank-level redundancy while sharing the physical space efficiently across the stacked architecture.
3Ease of manufacture
If wafer-to-wafer stacking is used, then low-cost integration is achieved, but stacked yield drops below 78%
Solution Approach 1:
The patent incorporates redundant banks and repair circuits before the stacking process, providing a cushion against potential defects that may occur during or after wafer-to-wafer stacking. This proactive redundancy ensures that even if stacking introduces defects, the overall yield remains above 95% through pre-configured backup resources.
Solution Approach 2:
The patent changes the operational parameters by implementing dynamic bank remapping and repair circuit activation based on detected defects. This adaptive approach allows the system to compensate for stacking-related yield losses by reconfiguring memory access patterns and activating redundant resources only when needed.
Data Source
AI summary
A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a base die, including a repair circuit. The 3D stacked memory package also includes memory dies stacked on the base die. The 3D stacked memory package further includes a package substrate supporting the base die. The 3D stacked memory package also includes data through silicon vias (TSVs) extending between the plurality of memory dies and landing on the base die. The data TSVs are shared on data (DQ) lines for each of the memory dies. Additionally, the repair circuit is configured to remap addresses of failed banks and/or pages across at least two different memory dies of the plurality of memory dies.