3D DRAM Bit Line Layout for Reduced Coupling During Sensing
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Solution Overview
Problem
The existing 3D DRAMs suffer from significant local bit line-to-bit line coupling issues, leading to a loss of sensing margin due to synchronous sense amplification of adjacent common bit lines.
Innovation Solution
The memory design includes a first chip with memory array tiles, where odd-numbered and even-numbered storage layer groups have distinct connections to common bit lines through bit line selectors and precharge switches, ensuring alternate sense amplification states and precharge potentials for adjacent bit lines, reducing coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If adjacent common bit lines undergo synchronous sense amplification, then memory access speed is improved, but bit line-to-bit line coupling increases and sensing margin is lost
Solution Approach 1:
The patent implements periodic alternating action by configuring odd-numbered and even-numbered storage layer groups to undergo sense amplification at different times. The bit line control circuit alternates between activating common bit lines from odd-layer groups and even-layer groups, ensuring that adjacent common bit lines do not undergo synchronous sense amplification. This periodic alternating pattern reduces capacitive coupling between adjacent bit lines while maintaining high memory access speed through efficient parallel operation of non-adjacent bit lines.
2Measurement precision
If bit line selectors and precharge switches are configured for alternating storage layer groups, then sensing margin is enhanced, but device complexity increases
Solution Approach 1:
The patent segments the storage layer groups into odd-numbered and even-numbered groups, with each group having dedicated bit line control circuits (bit line selectors and precharge switches). This segmentation allows independent control of adjacent common bit lines, enabling the sensing margin enhancement through alternating activation patterns while managing device complexity by organizing controls into systematic, repeatable units that can be scaled efficiently.
Solution Approach 2:
The bit line control circuit is designed with universal functionality to manage both odd-numbered and even-numbered storage layer groups. The same control circuit structure can selectively activate either odd-layer common bit lines or even-layer common bit lines based on the current operation requirements, reducing the need for completely separate control paths and thereby managing device complexity while achieving enhanced sensing margin.
Data Source
AI summary
The present disclosure provides a memory, a bit line control method, and an electronic device. In a first chip of the memory, each memory array tile includes multiple storage layer groups sequentially stacked in a third direction. In an odd-numbered storage layer group, each local bit line is coupled to a respective first common bit line through a respective bit line selector, and each local bit line is coupled to a respective second common bit line through a respective precharge switch. In an even-numbered storage layer group, each local bit line is coupled to a respective first common bit line through a respective precharge switch, and each local bit line is coupled to a respective second common bit line through a respective bit line selector.