3D DRAM Cache Integration with Tag Caches
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Solution Overview
Problem
Existing embedded DRAM (eDRAM) technology has a higher cost-per-bit compared to external DRAM and is limited in its ability to scale, hindering performance and efficiency in processor-memory integration.
Innovation Solution
The integration of three-dimensional (3D) DRAM with compute logic in the same package, utilizing multiple layers of DRAM cells connected via vias, and incorporating tag caches to reduce latency and improve cache access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional embedded DRAM is integrated on the same die as processor, then some performance advantages are achieved, but cost-per-bit is higher and scaling ability is limited
Solution Approach 1:
The patent transitions from planar 2D DRAM integration to 3D stacked DRAM architecture, where multiple DRAM layers are vertically stacked and connected via through-silicon vias (TSVs). This dimensional change enables significantly higher density and better scaling while maintaining close integration with the processor, thus improving performance without increasing cost-per-bit
2Quantity of substance
If 3D DRAM is stacked with compute logic in the same package, then large capacity caches are formed, but tag overhead and access latency increase
Solution Approach 1:
The patent divides the 3D DRAM cache into multiple independently accessible banks or slices, allowing parallel access operations. This segmentation enables the system to service multiple memory requests simultaneously, reducing the effective access latency despite the large total cache capacity
Solution Approach 2:
The patent introduces tag caches or directory structures that act as intermediaries between the processor and the large 3D DRAM cache. These intermediaries store metadata about cache contents, enabling faster lookup and reducing the time required to access data in the large capacity cache
3Quantity of substance
If multiple layers of DRAM cells are connected with vias, then cache capacity is increased, but manufacturing complexity increases
Solution Approach 1:
The patent employs universal TSV structures that serve multiple functions: they provide electrical connections between DRAM layers, act as mechanical support pillars, and enable thermal management. This multi-functionality reduces the need for additional specialized structures, thereby simplifying the overall manufacturing process despite the multi-layer architecture
Data Source
AI summary
Three-dimensional (3D) DRAM integrated in the same package as compute logic enable forming high-density caches. In one example, an integrated 3D DRAM includes a large on-de cache (such as a level 4 (L4) cache), a large on-die memory-side cache, or both an L4 cache and a memory-side cache. One or more tag caches cache recently accessed tags from the L4 cache, the memory-side cache, or both. A cache controller in the compute logic is to receive a request from one of the processor cores to access an address and compare tags in the tag cache with the address. In response to a hit in the tag cache, the cache controller accesses data from the cache at a location indicated by an entry in the tag cache, without performing a tag lookup in the cache.