3D DRAM Capacitor Pillar Manufacturing via Dual-Direction Etching
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Solution Overview
Problem
The miniaturization of DRAMs leads to reduced capacitor size, causing instability due to decreased charge storage capacity, and the formation of deep capacitor holes with high accuracy is challenging, often resulting in incomplete or defective holes and increased contact resistance.
Innovation Solution
A manufacturing method involving the formation of a pillar body with side surfaces parallel in different directions, covered by a conductive film, and etched to create a three-dimensional capacitor structure with a greater aspect ratio, using line-and-space patterns for precise photolithography and dry etching to increase capacitor capacity without expanding memory cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the capacitor size is reduced to achieve further integration, then the memory cell area is reduced, but the charge storage capacity is reduced causing unstable operation
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional structure by forming a hole through the insulation film and creating a storage electrode on the inner wall of the hole. This vertical dimension allows increased charge storage capacity without increasing the planar area occupied by the capacitor, thus resolving the contradiction between reducing memory cell area and maintaining charge storage capacity.
2Quantity of substance
If the capacitor hole is formed deeper to maintain charge storage capacity after size reduction, then the charge storage capacity is maintained, but the manufacturing precision deteriorates due to difficulty in forming deep holes with high accuracy
Solution Approach 1:
The patent introduces a catalyst layer as an intermediary between the insulation film and the storage electrode. This catalyst layer serves multiple functions: it facilitates the selective deposition of the storage electrode material on the inner wall of the hole, ensures uniform coating even in deep holes, and maintains manufacturing precision by providing a controlled interface for electrode formation. The catalyst layer enables accurate formation of deep capacitor holes with consistent charge storage capacity.
3Quantity of substance
If the capacitor hole is etched deeper to increase capacitor height, then the charge storage capacity is increased, but the contact resistance increases due to hole diameter reduction near the bottom
Solution Approach 1:
The patent creates a three-dimensional storage electrode structure that coats the inner wall of the hole rather than filling it completely. This approach maintains a sufficient hole diameter at the bottom for good contact with the capacitor contact plug while still achieving high charge storage capacity through the extended surface area of the inner wall. The catalyst layer ensures uniform electrode thickness throughout the hole depth.
Solution Approach 2:
The catalyst layer provides localized functionality at different positions within the hole. It ensures that the storage electrode is selectively formed on the inner wall surface while maintaining hole patency at the bottom. This local quality control allows the electrode to have optimal thickness and composition on the inner wall for charge storage, while the hole bottom remains open for low-resistance contact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of capacitors with enhanced charge storage capacity and reduced contact resistance by allowing deeper etching and increased capacitor height, maintaining performance without increasing memory cell size.
Implementation Method 1
a photolithography technique to form a hole pattern on a photoresist
Implementation Method 2
dry-etching the silicon oxide film using as mask the photoresist having the hole pattern formed thereon
Data Source
AI summary
A device manufacturing method includes forming a first insulation film on a semiconductor substrate. A first mask is formed on the first insulation film to extend in a first direction and have a linear pattern. The first insulation film is etched using the first mask as mask to process the insulation film into a linear body. A second mask is formed on the linear body to extend in a second direction different from the first direction and have a linear pattern. The linear body is etched using the second mask as mask to process the linear body into a pillar element. A first conductive film is formed to cover the pillar body. The first conductive film is etched to form a first electrode of the first conductive film on side surfaces of the pillar body.