3D DRAM Cell Structure With Stacked Transistor-Capacitor Alignment
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Solution Overview
Problem
Current vertical transistor techniques in Dynamic Random Access Memory (DRAM) face challenges such as high resistance in buried bit lines, parasitic coupling issues, alignment difficulties in wafer bonding, and limited thermal budgets due to high-temperature processes, which complicate the manufacturing process and affect the formation of air gaps and interconnect vias.
Innovation Solution
The method involves forming first portions of capacitors on a semiconductor substrate, stacking transistors over these portions, and then removing the substrate to form second portions of the capacitors by replacing sacrificial material, using irregularly shaped transistors and capacitors with angled gate structures, and forming bit lines on the surface, eliminating the need for buried bit lines and reducing thermal stress through sequence adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional vertical transistor techniques are used in DRAM, then manufacturing process can be simplified, but high resistance in buried bit lines and parasitic coupling issues occur
Solution Approach 1:
The patent transitions from planar bit lines to three-dimensional stacked structures, moving bit lines to different vertical levels above the substrate. This dimensional change eliminates the need for buried bit lines, reducing resistance and parasitic coupling while maintaining manufacturing feasibility through sequential deposition and patterning processes.
2Manufacturing precision
If high-temperature processes are used, then transistor formation can be improved, but thermal budget is limited and high-k material integrity is compromised
Solution Approach 1:
The patent performs transistor formation processes, including high-temperature steps, before depositing high-k dielectric materials. This preliminary action sequence ensures that temperature-sensitive high-k materials are not exposed to thermal damage, while still allowing optimal transistor formation to occur at earlier stages when thermal budget is available.
3Reliability
If wafer bonding is performed with aligned structures, then device integration is achieved, but alignment difficulties and process complexity increase
Solution Approach 1:
The patent employs asymmetric transistor footprints and irregularly shaped capacitor structures with specific geometric features that serve as self-alignment references. These asymmetric designs create unique alignment markers that simplify wafer bonding registration, reducing alignment complexity while ensuring precise device integration.
4Quantity of substance
If narrow pitch structures are used, then memory density is increased, but formation of air gaps and interconnect vias becomes more difficult
Solution Approach 1:
The patent divides the capacitor structures into segmented portions with spaced-apart components, creating natural air gaps between segments. This segmentation approach maintains narrow pitch for high density while ensuring sufficient spacing for air gap formation and via access, enabling manufacturing of dense structures without compromising process feasibility.
Data Source
AI summary
Systems, devices, and methods for managing three-dimensional (3D) semiconductor devices are provided. In one aspect, a semiconductor device includes an array structure having a plurality of memory cells. A memory cell of the plurality of memory cells includes a transistor and a capacitor that are stacked together. The transistor includes a transistor body, a first terminal, a second terminal, and a gate structure. The first terminal of the transistor is in contact with a first electrode of the capacitor along the first direction. The gate structure includes a conductive film having an angled or curved end closer to the first terminal of the transistor than the second terminal of the transistor.