3D Vertical DRAM Cell Stacking for Higher Logic Density
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Solution Overview
Problem
Conventional 2D semiconductor device manufacturing techniques are limited by physical atomic constraints, leading to challenges in increasing transistor density, as they rely on flat substrate surfaces for both transistors and capacitors in memory cells, occupying valuable space and hindering further miniaturization.
Innovation Solution
The implementation of a 3D vertically stacked capacitor-based memory cell design, where a capacitor and a transistor are stacked vertically, allowing for a DRAM cell to occupy space typically used by only one device, utilizing a vertically-oriented cylindrical field-effect transistor and a cylindrically-shaped capacitor with dielectric material for insulation, enabling increased density without requiring epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If 2D fabrication techniques are used to manufacture memory circuits on a substrate, then the manufacturing process is simple and well-established, but the transistor density per unit area is limited due to physical atomic constraints
Solution Approach 1:
The patent transitions from 2D planar fabrication to 3D vertical stacking by forming trenches through the substrate and stacking memory cells vertically along the depth dimension. This dimensional change allows multiple transistor-capacitor pairs to occupy the same footprint area, dramatically increasing density while maintaining compatibility with conventional fabrication processes
2Device complexity
If 2D arrangement of transistor and capacitor is used in DRAM cell, then the circuit implementation is straightforward, but the substrate surface area required is large
Solution Approach 1:
The patent stacks the capacitor vertically above the transistor within a shared trench structure, transitioning from lateral 2D placement to vertical 3D stacking. This allows both components to occupy the same horizontal footprint while maintaining electrical connectivity, reducing the substrate area per cell by approximately half compared to 2D layouts
3Ease of manufacture
If conventional trench-based configuration is used for DRAM cell, then the manufacturing process is well-established, but the number of transistors per unit area cannot be increased further
Solution Approach 1:
The patent divides the substrate into multiple vertical columns or pillars, each containing a stacked transistor-capacitor pair. This segmentation allows independent fabrication of each stack using conventional processes, while the collective array achieves high density through vertical multiplication of cells per unit area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the number of semiconductor circuits per unit area, overcoming the limitations of 2D fabrication by allowing for higher density semiconductor devices without the need for epitaxial growth, enabling efficient high-density logic and circuit design.
Implementation Method 1
A dielectric material layer can be disposed between the outer surface of the first metal rod-shaped component and the interior surface of the interior cavity of the second component into which the first component is formed or inserted. The dielectric material layer can electrically insulate and maintain a distance apart between the first and the second metal components
Data Source
AI summary
Apparatuses, devices, and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.