3D DRAM CMOS-Between-Array Layout for Lower Bit Line Loading
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Solution Overview
Problem
Conventional 3D DRAM architectures face challenges in reducing parasitic loading, mechanical stress, and area consumption due to the stacking of memory arrays and CMOS layers, which complicates etching processes and increases bit line pitch.
Innovation Solution
A CMOS-between-array (CbA) architecture is introduced, where the CMOS layer is positioned between two memory arrays, allowing for reduced parasitic loading, mechanical stress, and area consumption by optimizing the arrangement of word lines and bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the CMOS layer is stacked adjacent to the memory array in conventional 3D DRAM architectures, then the memory cell density is increased, but the parasitic loading increases and etching process becomes more complicated
Solution Approach 1:
The patent divides the memory array into two separate arrays and positions the CMOS layer between them, rather than stacking one array on top of the CMOS layer. This segmentation approach reduces the height of the hole etch process while maintaining high memory cell density through vertical stacking of the two arrays.
Solution Approach 2:
The patent transitions from a single-sided stacking architecture to a dual-sided architecture where memory arrays are positioned on both sides of the CMOS layer along the vertical axis. This dimensional reorganization reduces the etch hole height while preserving storage capacity through symmetric vertical stacking.
2Quantity of substance
If the memory array and CMOS layer are stacked to increase storage capacity, then the storage density is improved, but the mechanical stress increases
Solution Approach 1:
By dividing the memory structure into two separate arrays positioned on opposite sides of the CMOS layer, the patent distributes the mechanical stress more evenly throughout the structure. This segmentation prevents stress concentration that would occur in single-sided stacking configurations.
Solution Approach 2:
The dual-sided symmetric stacking creates a balanced structure where the two memory arrays act as counterweights, distributing mechanical stress uniformly across the CMOS layer and reducing overall stress accumulation in the stacked structure.
3Quantity of substance
If the bit line pitch is reduced to increase memory cell density, then the storage capacity is improved, but the area consumption increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking two memory arrays above and below the CMOS layer, allowing high storage capacity to be achieved without proportionally increasing the planar area. This vertical expansion enables reduced bit line pitch while maintaining acceptable area consumption through three-dimensional architecture.
Data Source
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AI summary
The present disclosure relates to a 3D dynamic random access memory (DRAM). The 3D DRAM of this disclosure comprises a CMOS-between-array (CbA) architecture. The DRAM comprises a first memory array, a second memory array, and a CMOS layer comprising circuitry for operating the first memory array and the second memory array, respectively. The CMOS layer is arranged between the first memory array and the second memory array along a first axis. The circuitry of the CMOS layer comprises one or more word line drivers configured to drive word lines associated with respectively the first memory array and the second memory array, and comprises one or more sense amplifiers configured to sense charge on bit lines respectively associated with the first memory array and the second memory array.