3D DRAM Memory Structure with Columnar Channels for Density Scaling
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Solution Overview
Problem
Conventional DRAMs face challenges in miniaturization and process complexity, with increasing capacitor aspect ratios, necessitating a new memory structure and manufacturing method to overcome these issues.
Innovation Solution
A 3D dynamic random access memory structure with a 2T0C design, featuring alternating insulating and gate layers, doping layers, and dielectric layers, allowing for high-density memory cells with a simplified manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 1T1C DRAM structure is used, then manufacturing process is relatively simple, but memory density is low and device size cannot be easily miniaturized
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional vertical stacking architecture. Multiple insulating layers and gate layers are stacked vertically to form multiple memory cells in the vertical dimension, enabling higher memory density without increasing footprint area. The columnar channel structure extends vertically through multiple layers, utilizing the third dimension for scaling.
Solution Approach 2:
The patent implements nested structures where columnar channels are surrounded by doping layers, which are in turn surrounded by dielectric layers and gate layers. The alternating insulating and gate layers are nested around the columnar channel structure, creating a compact multi-layer configuration that maximizes space utilization.
2Volume of moving object
If DRAM size is reduced, then memory density improves, but capacitor aspect ratio increases dramatically
Solution Approach 1:
The patent eliminates traditional capacitor structures by using a 2T0C (two-transistor, zero-capacitor) design. Data is stored in the doping layers that surround the columnar channel, replacing the conventional capacitor entirely. This approach avoids the aspect ratio problem while achieving miniaturization through vertical stacking.
Solution Approach 2:
The patent extracts and removes the capacitor component from the traditional 1T1C DRAM structure. By using doping layers integrated with the channel structure to store charge, the design eliminates the need for separate capacitor structures, thereby avoiding the aspect ratio issue that plagues scaled-down conventional DRAMs.
3Productivity
If alternating insulating and gate layers are stacked vertically, then memory density increases, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the memory structure into repeating units of insulating layers and gate layers that can be manufactured using standard semiconductor fabrication processes. Each layer pair forms a discrete memory cell, allowing for modular manufacturing and scaling. The columnar channels are formed by patterning and filling processes that can be integrated into existing CMOS fabrication lines.
Solution Approach 2:
The gate layers serve multiple functions: they control the channel conductivity for transistor operation and also form part of the memory cell structure for charge storage. The doping layers simultaneously provide electrical doping functionality and serve as the charge storage mechanism, replacing the traditional capacitor. This multi-functionality reduces the number of separate components needed.
Data Source
AI summary
A memory structure includes insulating layers, gate layers, a first doping layer, channel layers, a columnar channel, second doping layers, a first dielectric layer, second dielectric layers, a third dielectric layer, and fourth dielectric layers. The first doping layer and the columnar channel penetrate through the insulating layers and the gate layers that are alternately stacked. The channel layers are connected to the first doping layer, in which the channel layers and the insulating layers are alternately stacked. The second doping layers surround the columnar channel and are connected to the channel layers. The first dielectric layer is between the first doping layer and the gate layers. The second dielectric layers are between the second doping layers and the gate layers. The third dielectric layer is between the columnar channel and the second doping layers. The fourth dielectric layers are between the channel layers and the gate layers.