3D DRAM Control Logic Vertical Stacking for Routing Efficiency
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Solution Overview
Problem
Three-dimensional (3D) memory device architectures face challenges with complex and congested routing designs to electrically connect DRAM cells to control logic circuitry, such as sub-word line drivers (SWD) and sense amplifiers (SA) circuitry.
Innovation Solution
The solution involves reconfiguring the layout of control logic circuitry, such as SWD and SA sections, to be vertically overlapping and in electrical communication with sub-word line exit regions and word line exit regions, respectively, while maintaining lateral bounded electrical communication within socket regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic circuitry is placed in a base control logic structure underlying the memory array, then electrical connection to DRAM cells is achieved, but routing becomes complex and congested in 3D architectures
Solution Approach 1:
The patent transitions from a planar routing approach to a three-dimensional routing architecture by placing control logic circuitry (SWD and SA sections) in multiple stacked layers above the memory array. This vertical stacking enables direct electrical connections through contact holes while distributing routing paths across multiple levels, thereby reducing congestion in any single plane and simplifying the overall routing design.
Solution Approach 2:
The control logic circuitry is segmented into distinct functional blocks: sub-word line driver (SWD) sections and sense amplifier (SA) sections, which are distributed across multiple layers. Each segment handles specific routing tasks independently, reducing the complexity of any single routing path and enabling more efficient signal distribution throughout the memory array.
2Reliability
If complex routing designs are used to connect DRAM cells to control logic circuitry, then electrical connectivity is achieved, but timing delays increase
Solution Approach 1:
By implementing vertical stacking of control logic sections across multiple layers, the patent creates shorter electrical paths through direct vertical connections via contact holes. This three-dimensional arrangement eliminates the need for long lateral routing paths that would otherwise increase signal propagation delay, thereby improving timing performance while maintaining electrical connectivity.
Solution Approach 2:
The control logic circuitry is pre-positioned in specific layers above the memory array during device fabrication, with contact holes pre-formed to establish electrical connections. This preliminary arrangement of control sections and routing paths ensures optimal signal routing is built-in from the start, minimizing timing delays without requiring post-fabrication adjustments.
3Productivity
If control logic circuitry is reconfigured to vertically overlapping positions, then routing efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent employs standard semiconductor fabrication techniques for creating vertically stacked structures, including sequential deposition of sacrificial layers, formation of contact holes through etching, and deposition of interlayer dielectrics. These are well-established processes that can be integrated into existing manufacturing lines, making the vertical stacking approach manufacturable while achieving improved routing efficiency.
Solution Approach 2:
The control logic sections are nested within the vertical profile of the memory array structure, with SWD and SA sections positioned in intermediate layers between the memory array and the top surface. This nesting approach allows compact integration of multiple functional blocks within the device footprint while using standard fabrication sequences that maintain ease of manufacture.
Data Source
AI summary
A microelectronic device is disclosed that includes array regions individually comprising memory cells comprising access devices and storage node devices; digit lines coupled to the access devices and extending in a first direction; and word lines coupled to the access devices and extending in a second direction orthogonal to the first direction, and the word lines extend into word line exit regions. The word line exit regions are horizontally alternating with the array regions in the second direction; and sub word line driver sections are overlapping and above, and in electrical communication with the word line exit regions. Electrical communication between word lines in the word line exit regions and the sub word line driver sections vertically coupled with a vertical word line contact and other interconnections is laterally bounded within socket regions delineated by horizontal boundaries of the word line exit regions.