3D DRAM Cylindrical Capacitor Structure for Higher Integration
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration density and large capacitor capacity due to structural limitations, particularly in three-dimensional dynamic random access memories (3D DRAMs).
Innovation Solution
A semiconductor device with a stack structure featuring cylindrical first electrodes supported by a support structure, surrounded by a dielectric layer and a second electrode layer, allowing for longer electrodes and improved integration through the use of connecting parts and conductive filling layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the structure size is shrunk to achieve higher integration density, then the integration density is improved, but the technical barrier becomes more obvious and manufacturing difficulty increases
Solution Approach 1:
The patent transitions from planar electrode structures to three-dimensional cylindrical electrodes stacked vertically. The cylindrical first electrodes are arranged in multiple stacks along the first direction (vertical to substrate), with each electrode having a second end opening connected to support structures. This dimensional change enables higher integration density by utilizing the vertical space more effectively, allowing more capacitor structures to be packed into a smaller footprint on the substrate.
Solution Approach 2:
The patent implements a nested structure where the first dielectric layer is deposited inside the cylindrical first electrodes, and the second electrode layer is formed surrounding the first dielectric layer. The support structures are positioned within the spaces between cylindrical electrodes, creating a compact nested arrangement. This nesting approach maximizes space utilization and enables higher integration density without proportionally increasing the overall device footprint.
2Quantity of substance
If conventional electrode structures are used, then manufacturing is simpler, but capacitor capacity is limited and integration density cannot be sufficiently increased
Solution Approach 1:
The patent segments the electrode structure into multiple cylindrical first electrodes, each with a second end opening connected to separate support structures. Each cylindrical electrode is independently formed and can be independently processed. The first dielectric layer is deposited inside each cylinder, and the second electrode layer is formed surrounding each cylinder. This segmentation allows for modular manufacturing and enables increased capacitor capacity by adding more cylindrical electrode units without requiring complete redesign of the entire device.
Solution Approach 2:
The patent performs preliminary actions by forming the cylindrical first electrodes and their second end openings before depositing the first dielectric layer and forming the second electrode layer. The support structures are positioned in advance within the spaces between cylindrical electrodes. This preliminary structuring enables subsequent dielectric and electrode layer deposition to proceed more efficiently, maintaining manufacturing simplicity while achieving higher capacitor capacity through the pre-established cylindrical geometry.
3Quantity of substance
If longer cylindrical electrodes are used to increase capacitor capacity, then the capacitor capacity is improved, but the chip space occupied by the capacitor increases
Solution Approach 1:
The patent resolves the space-capacity contradiction by transitioning from planar to three-dimensional electrode arrangements. The cylindrical first electrodes extend along the second direction (horizontal) while being stacked along the first direction (vertical). The second end openings are positioned at the top of each cylinder, allowing vertical stacking of multiple electrodes in the same horizontal footprint. This dimensional change enables longer effective electrode length for increased capacitor capacity without proportionally increasing the chip area, as multiple electrodes share the same horizontal space vertically.
Solution Approach 2:
The patent implements nesting by placing the first dielectric layer inside the cylindrical first electrodes and the second electrode layer surrounding the first dielectric layer, creating a compact concentric structure. The support structures are nested within the spaces between cylindrical electrodes. This nested arrangement maximizes the utilization of available space, allowing longer cylindrical electrodes for increased capacitor capacity while minimizing the overall chip area occupied, as the nested structure eliminates wasted space between electrode components.
Data Source
AI summary
Provided are a semiconductor device, a method for manufacturing the same, and a three-dimensional dynamic random access memory. The semiconductor device includes a substrate and a stack structure disposed on the substrate. The stack structure includes a support structure and memory cells stacked along a first direction. Each of the memory cells includes a cylindrical first electrode extending along a second direction; the first electrode includes a first end and a second end along the second direction, the first end is blind, and the second end has an opening and is connected to the support structure. The support structure includes a first part surrounding a part of an outer surface of the first electrode.