3D DRAM Stacked Structure Etching With Substrate Protection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The manufacturing processes for multilayer stacked transistors and capacitors in 3D DRAMs face challenges such as complex etching and filling processes, leading to high difficulty and low device yield, with etching agents causing substrate erosion and structural instability.

Innovation Solution

A method involving selective etching and protective layer formation to expose sacrificial layers while protecting the substrate, using silicon nitride as a barrier layer and silicon oxide as a protective layer to prevent substrate damage during etching, followed by deposition of capacitor materials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional etching processes are used to remove sacrificial layers in 3D DRAM manufacturing, then the etching and filling processes can be completed, but substrate erosion and structural instability occur leading to low device yield

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoiddevice yield
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A protective layer is introduced as an intermediary between the etching agent and the substrate. This protective layer selectively protects the substrate from etching damage while allowing the etching agent to access and remove the sacrificial layers through designated regions, thereby preventing substrate erosion and improving device yield without compromising manufacturing efficiency

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protective layer is selectively formed in specific regions where substrate protection is needed, rather than uniformly across the entire substrate. This localized protection approach allows the etching process to proceed in targeted areas while preserving the substrate in critical regions, resolving the contradiction between complete etching and substrate integrity

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If complex multilayer stacking processes are used to achieve high integration density, then more transistors and capacitors can be integrated, but the manufacturing process complexity increases leading to low device yield

Engineering Contradiction:
Improveintegration densityVSAvoidprocess complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The protective layer is formed in advance before the etching process, preparing the substrate for selective etching. This preliminary action simplifies the subsequent etching steps by pre-defining protected regions, thereby reducing overall process complexity while maintaining high integration density capabilities

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The manufacturing process is segmented into distinct stages: protective layer formation, selective etching of sacrificial layers, and subsequent filling. This segmentation breaks down the complex multilayer stacking process into manageable steps, improving device yield while achieving high integration density

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If sacrificial layers are removed through etching to form capacitor structures, then the capacitor structures can be formed, but substrate damage occurs compromising structural stability

Engineering Contradiction:
Improvecapacitor structure formationVSAvoidsubstrate stability
Core Design Contradiction:
Ease of manufactureVSStability of the object's composition

Solution Approach 1:

The protective layer serves as a mediator that enables the etching process to proceed without directly contacting and damaging the substrate. It allows easy formation of capacitor structures through selective etching while simultaneously protecting the substrate from damage, maintaining structural stability

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260052672A1Method for manufacturing semiconductor structure and semiconductor structure
Publication Date: 2026.02.19 RUILI INTEGRATED CIRCUIT CO LTD
  • US20260052672A1 patent drawing
  • US20260052672A1 patent drawing
  • US20260052672A1 patent drawing

AI summary

A method for manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method includes the steps as follows. A substrate is provided, where the substrate includes a first region and a second region. A stacked structure with multiple first material layers and multiple second material layers alternately stacked is formed on the first region. First etching is performed to form a groove at one end of the stacked structure, the second region being exposed at the bottom of the groove. Second etching is performed, to remove a part of the multiple second material layers through the groove, and retain the multiple first material layers arranged at intervals. Before the second etching is performed, the method further includes the step as follows. A protective layer is formed on a surface of the second region, where the protective layer further extends toward at least a surface of the first region.