3D DRAM Gate Isolation Structure for Uniform Gate Thickness
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Solution Overview
Problem
In three-dimensional dynamic random access memory (DRAM) structures, there is a challenge in achieving uniform thickness between gate layers, limited selection of barrier materials, and significant capacitive coupling between adjacent gate layers, which affects memory performance and manufacturing complexity.
Innovation Solution
A method involving the formation of first isolation structures with specific through holes and pillars, followed by the deposition of a barrier layer and gate layers, ensures uniformity and improved isolation between gate layers, using self-aligned processes to simplify the manufacturing process and expand material selection for the barrier layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional barrier layer materials (silicon oxide) are used in three-dimensional memory structures, then the manufacturing process is simplified, but the isolation effect between adjacent gate layers deteriorates and capacitive coupling increases
Solution Approach 1:
The patent employs a composite barrier layer structure consisting of multiple materials (e.g., silicon oxide combined with silicon nitride or other dielectric materials) to achieve both good isolation effect and manufacturing feasibility. This composite approach allows the barrier layer to provide effective electrical isolation between adjacent gate layers while maintaining compatibility with existing manufacturing processes.
2Quantity of substance
If three-dimensional memory structures are adopted to increase storage density, then the memory capacity is improved, but the thickness uniformity between adjacent gate layers deteriorates
Solution Approach 1:
The patent segments the barrier layer formation process into multiple controlled steps, including forming through-holes in isolation structures, depositing barrier materials in specific patterns, and selectively removing portions. This segmentation allows precise control over the barrier layer thickness and position, thereby improving the overall thickness uniformity of gate layers in three-dimensional memory structures.
Solution Approach 2:
The patent performs preliminary actions by first forming isolation structures with through-holes before depositing the gate layers. The barrier layer is pre-formed in these through-holes to establish a foundation that ensures uniform thickness distribution. This preliminary barrier layer formation guides subsequent gate layer deposition and helps maintain consistent thickness across the three-dimensional structure.
3Ease of manufacture
If material selection for barrier layers is limited to traditional options, then the manufacturing process remains simple, but the isolation performance and memory performance are reduced
Solution Approach 1:
The patent changes the material parameters of the barrier layer by introducing alternative dielectric materials with different electrical and physical properties. By selecting materials with appropriate permittivity, breakdown strength, and etch selectivity, the patent optimizes both the isolation performance and overall memory device performance while maintaining manufacturability through adapted deposition and etching processes.
Data Source
AI summary
A method for forming a memory includes the following operations: a substrate and a semiconductor layer located on the substrate are formed; the semiconductor layer is patterned to form a plurality of first isolation structures and channel regions, each first isolation structure includes a first through hole and a second through hole, and a first isolation pillar located between the first through hole and the second through hole; a first filling layer filling up the first through hole and the second through hole is formed; the first isolation pillar is removed to form a third through hole located in the first filling layer; a barrier layer filling up the third through hole is formed; the channel regions are exposed by removing the first filling layer; and a gate layer covering surfaces of the channel regions is formed.