3D DRAM Memory Cell Array Over Driver Circuit for Higher Density
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Solution Overview
Problem
Current DRAM memory devices face challenges in increasing memory capacity per unit area while maintaining a high integration degree of integrated circuits without increasing chip size.
Innovation Solution
The semiconductor memory device incorporates a memory cell array overlapping with a driver circuit containing a single crystal semiconductor substrate, utilizing a multilayer wiring layer with copper or copper alloy wirings, and featuring memory cells with transistors having oxide semiconductor channel regions and capacitors with one electrode connected to the transistor's source or drain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single crystal semiconductor substrate is used for high integration degree, then device reliability is improved, but chip size increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by forming memory cell arrays and driver circuits in different layers (first and second semiconductor substrates) stacked in the vertical direction. This allows high integration without increasing chip area while maintaining single crystal semiconductor reliability in each layer.
Solution Approach 2:
The patent divides the semiconductor device into multiple independent single crystal semiconductor substrates (first and second substrates) that are stacked and bonded together. Each substrate can be separately manufactured and tested, then bonded to form the complete device, achieving high integration without increasing individual chip size.
2Quantity of substance
If capacitor area is reduced to increase memory capacity per unit area, then memory capacity is improved, but capacitor performance deteriorates
Solution Approach 1:
The patent forms capacitors in the vertical direction (stacked configuration) rather than expanding them horizontally. Capacitor electrodes are stacked above each other with insulating layers in between, increasing capacitance without increasing planar area, thus maintaining memory capacity while preserving capacitor performance.
Solution Approach 2:
The patent implements trench capacitors where capacitor electrodes are nested within trenches formed in the semiconductor substrate. This nested structure allows the capacitor to occupy vertical space within the substrate, increasing memory capacity per unit area while maintaining adequate capacitor performance through proper trench depth and electrode configuration.
3Adaptability or versatility
If multilayer wiring is implemented to connect highly integrated semiconductor elements, then connectivity is improved, but wiring resistance increases
Solution Approach 1:
The patent uses copper wiring specifically in the multilayer wiring structure where low resistance is critical for connecting highly integrated semiconductor elements. Copper's superior electrical conductivity compensates for the increased wiring path length in multilayer configurations, maintaining low overall wiring resistance while providing the needed connectivity.
Solution Approach 2:
The patent employs composite wiring structures combining copper layers with barrier layers (such as tungsten or tantalum nitride) to prevent copper diffusion while maintaining low resistance. This composite approach enables multilayer wiring with excellent connectivity and minimized energy loss through optimized material combinations.
4Quantity of substance
If oxide semiconductor transistors are used to reduce capacitor area, then memory capacity is improved, but transistor mobility decreases
Solution Approach 1:
The patent uses oxide semiconductor transistors specifically in memory cell regions where small area is critical, while employing conventional high-mobility transistors in driver circuit regions where high speed is critical. This local differentiation allows the system to achieve high memory capacity through compact oxide semiconductor cells while maintaining overall device performance through conventional transistors in the driver circuits.
Data Source
AI summary
The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.