3D DRAM Cell Stacking With Low-Temperature Oxide Transistors
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in scaling transistors beyond single-digit nanometer nodes, where traditional two-dimensional (2D) circuits face limitations in increasing transistor density, prompting the need for three-dimensional (3D) integration by stacking transistors vertically to enhance circuit density and overcome scaling challenges.
Innovation Solution
The development of a semiconductor device with vertically stacked dynamic random access memory (DRAM) cell units, comprising a transistor and a capacitor, where the capacitor is elongated horizontally and the transistor has a channel structure with a gate structure disposed around it, allowing for increased density and efficient electrical connections, and the use of semiconducting oxides and 2D semiconductor materials to facilitate current flow and reduce processing temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high-temperature processing is used to form semiconductors, then semiconductor devices can be manufactured, but existing transistors are damaged during processing
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature processing to low-temperature processing (below 450°C, preferably below 400°C). This is achieved by using atomic layer deposition (ALD) to form semiconducting oxide layers that can be processed at these lower temperatures, thereby preventing damage to existing transistors while still forming functional semiconductor devices.
Solution Approach 2:
The patent employs semiconducting oxides (such as In2O3, SnO2, ZnO) as composite material alternatives to conventional silicon-based semiconductors. These oxides can be deposited and processed at low temperatures using ALD, enabling formation of new transistor layers without requiring high-temperature processing that would damage existing devices.
2Productivity
If 3D vertical stacking is implemented to increase circuit density, then transistor density improves, but fabrication complexity increases
Solution Approach 1:
The patent transitions from 2D planar circuits to 3D vertical stacking by forming multiple layers of transistors and capacitors stacked in the vertical direction. Each layer is formed using sequential ALD deposition steps, allowing circuit density to increase by utilizing the third dimension while maintaining compatibility with existing fabrication processes.
Solution Approach 2:
The patent divides the 3D structure into discrete, independently formable layers including semiconducting oxide layers, metal electrode layers, dielectric layers, and conductive bridge layers. Each layer can be formed and processed separately using ALD, simplifying the overall fabrication by breaking down the complex 3D structure into manageable sequential steps.
3Manufacturing precision
If seed layers are required for semiconductor growth, then crystal quality improves, but manufacturing steps increase
Solution Approach 1:
The patent removes the requirement for seed layers by using atomic layer deposition (ALD) to directly form high-quality semiconducting oxide crystalline structures on various substrates. The ALD process inherently provides atomic-level control and surface preparation, eliminating the need for separate seed layer deposition steps while maintaining crystal quality.
Solution Approach 2:
The semiconducting oxide materials (In2O3, SnO2, ZnO) possess inherent properties that allow them to form high-quality crystalline structures directly during ALD processing without requiring external seed layers. The materials self-organize into functional semiconductor structures through the controlled deposition process, reducing fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of highly dense 3D memory circuits with reliable access transistors and nanosheet transistors, allowing for hierarchical stacking and efficient electrical connections, thereby overcoming the limitations of traditional 2D circuits and enabling the formation of N-tall DRAM memory cells without limits.
Implementation Method 1
deposited via ALD, to create horizontal DRAM cells with metal capacitors and nanosheet transistors
Data Source
AI summary
A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. At least one DRAM cell unit includes a transistor and a capacitor. The capacitor includes a first metal layer, a capacitor dielectric layer positioned on the first metal layer, and a second metal layer positioned on the capacitor dielectric layer. The capacitor is elongated in a horizontal direction parallel to the working surface of the substrate. The second metal layer has a first end and a second end in the horizontal direction. The transistor includes a channel structure, and a gate structure disposed all around the channel structure. The first metal layer extends in the horizontal direction beyond the first end of the second metal layer to form a drain region and a source region of the transistor.