3D DRAM Sense Amplifier Layout for Congestion Relief
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Solution Overview
Problem
Three-dimensional (3D) microelectronic device architectures, such as 3D DRAM devices, face complex and congested routing designs due to the need to electrically connect DRAM cells to control logic circuitry, leading to performance challenges.
Innovation Solution
The implementation of a microelectronic device design that includes a unique arrangement of digit line and word line exit regions, along with sense amplifier and sub-word line driver configurations, to facilitate efficient electrical connections between DRAM cells and control logic circuitry, reducing routing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic circuitry is placed underlying memory arrays in conventional 3D architectures, then electrical connection between DRAM cells and control logic is established, but routing congestion increases and performance deteriorates
Solution Approach 1:
The patent transitions from a planar routing architecture to a three-dimensional routing architecture by introducing vertical routing structures (through-silicon vias, contact holes) that extend in the Z-direction. This allows signals to travel vertically between memory arrays and control logic circuitry rather than relying solely on horizontal routing paths, significantly reducing routing congestion and improving electrical connectivity in 3D memory devices.
Solution Approach 2:
The patent divides the memory device into distinct functional layers: memory array layers and control logic circuitry layers, separated by intermediate routing layers. This segmentation allows independent optimization of each layer's routing paths and enables parallel signal transmission through multiple vertical routing channels, reducing overall routing complexity and congestion.
2Reliability
If complex routing designs are used to connect DRAM cells to control logic in 3D architectures, then electrical connectivity is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent employs universal vertical routing structures (through-silicon vias and contact holes) that serve multiple functions: connecting memory cells to control logic, providing mechanical support between layers, and enabling thermal management. This multi-functionality simplifies the manufacturing process by using a single routing approach for multiple purposes rather than requiring specialized structures for each function.
Solution Approach 2:
The patent optimizes routing parameters such as via diameter, contact hole size, and routing layer thickness to achieve the required electrical connectivity while maintaining manufacturability. By carefully controlling these geometric parameters within standard fabrication capabilities, the patent achieves complex 3D connectivity without requiring advanced or costly manufacturing processes.
Data Source
AI summary
A microelectronic device is disclosed including a control logic structure that includes sense amplifiers clustered around sense amplifier exit regions; an upper memory array structure underlying the control logic structure and that includes memory cells coupled to some of the sense amplifiers of the control logic structure by way of routing extending through the sense amplifier exit regions; and a lower memory array structure underlying the upper memory array structure and that includes additional memory cells coupled to some other of the sense amplifiers of the control logic structure by way of additional routing extending through the sense amplifier exit regions.