3D DRAM Row Counters for Threshold-Based Hammer Mitigation
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Solution Overview
Problem
Repeated row activations in dynamic random access memory (DRAM) cause neighboring cells to lose stored values, a phenomenon known as 'row hammer,' which affects storage reliability.
Innovation Solution
A 3D DRAM architecture with counters and control circuits under the memory cell array tracks row hammer events, refreshing affected rows when a threshold is reached, either immediately or as part of a regular refresh sequence, and preventing further access until the refresh is complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If row hammer mitigation counters and control circuits are added under the memory cell array, then storage reliability is improved, but device complexity increases
Solution Approach 1:
The counter circuitry is merged with the memory array structure by placing counters underneath the memory cell array, with each counter associated with a corresponding memory row. This integration allows the mitigation function to be added without requiring separate external circuitry, thus improving reliability while controlling the increase in device complexity through spatial consolidation.
2Reliability
If row refresh operations are performed immediately when threshold is reached, then storage reliability is improved, but productivity decreases
Solution Approach 1:
The refresh operation timing is made dynamic based on system conditions. When a row hammer threshold is detected, the control circuitry can schedule the refresh operation at an optimal time rather than immediately, allowing normal memory operations to continue uninterrupted. This dynamic scheduling ensures data integrity while minimizing impact on memory throughput and overall system productivity.
3Measurement precision
If counters track all row activations, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The counter circuitry is implemented with a localized structure where each counter is positioned underneath its corresponding memory row, creating a direct one-to-one mapping. This local quality approach allows precise tracking of row hammer events for each specific row without requiring global monitoring circuitry, thereby achieving high measurement precision while keeping the added complexity distributed and manageable across the memory array structure.
Data Source
AI summary
A 3D DRAM architecture may have one or more layers of cells where the access transistors of the memory cell array are fabricated among the metal layers rather than in the semiconductor (e.g., silicon) substrate. Counter and counter control circuits for each row in the memory cell array are fabricated under the array. These counters track the number of row hammers each row experiences. When a counter indicates a row has experienced a threshold number of row hammers, that row is refreshed. The row may be refreshed immediately after the current row is closed. The row may be scheduled to be refreshed as part of a regular refresh sequence. A signal may be sent to the memory controlling indicating that the bank with the row being refreshed immediately should not be accessed until the refresh is complete.