3D DRAM Cell Structure for Row Hammer and Current Retention
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Solution Overview
Problem
The challenge in semiconductor memory devices is to improve the degree of integration of memory cells while addressing issues such as the Row hammer effect and decreasing drain current as the device size scales down, particularly in three-dimensional DRAM structures.
Innovation Solution
The semiconductor memory device features a three-dimensional structure with vertically stacked layers, including active regions, conductive lines, and capacitors, where bit lines are interposed between word lines to reduce interference and gate electrode layers are coupled to channel regions to slow down current drops, facilitating better data retention and scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are scaled down to improve integration density, then the degree of integration is improved, but the Row hammer effect increases and drain current decreases
Solution Approach 1:
The patent transitions from planar memory cell layout to a three-dimensional stacked structure where memory cells are arranged vertically across multiple layers. Bit lines extend vertically through the substrate to connect to capacitors in upper layers, while word lines are arranged horizontally in each layer. This vertical stacking enables higher integration density without further scaling of individual cell dimensions, thereby maintaining reliability by preserving adequate current drive capability and reducing Row hammer effects through increased physical separation.
2Quantity of substance
If device size is reduced to increase memory cell density, then integration is improved, but drain current decreases
Solution Approach 1:
By stacking memory cells vertically in multiple layers rather than expanding horizontally, the patent achieves higher cell density while maintaining larger individual transistor dimensions. This allows sufficient drain current to flow through each transistor while packing more cells per unit area through the vertical dimension. The bit lines extending vertically provide low-resistance pathways that compensate for any current limitations.
3Quantity of substance
If memory cells are stacked vertically to improve integration, then device density is improved, but structural complexity increases
Solution Approach 1:
The patent divides the memory device into multiple discrete layers, with each layer containing a subset of the memory cell components (word lines, capacitors, portions of bit lines). This segmentation allows for modular manufacturing processes where each layer can be formed and processed separately, then stacked together. The vertical bit lines act as interconnect structures that penetrate through multiple layers, providing a systematic approach to managing the complexity of three-dimensional interconnections.
Data Source
AI summary
A semiconductor memory device includes a substrate, and a plurality of layers vertically stacked over the substrate. A first layer in the plurality of layers includes an active region extending in a first direction parallel to a top surface of the substrate. The semiconductor memory device also includes a first conductive line that extends vertically in a second direction perpendicular to the top surface of the substrate and penetrates through the active region. The semiconductor memory device also includes a capacitor including a first electrode that is disposed in the active region.