3D-Stacked DRAM Access Through Direct Sense Amplifier Coupling
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Solution Overview
Problem
Conventional DRAM access methods are limited by the two-dimensional layout, leading to long column select lines and main data lines that restrict the number of memory cells that can be accessed simultaneously, resulting in reduced bandwidth and increased access time due to the density of cell arrays.
Innovation Solution
The implementation of a memory device using three-dimensional chip stacking technology, where a system on chip (SoC) directly connects to a first sense amplifier in different dies through hybrid bonding, allowing for simultaneous access to multiple memory cells via a single command, thereby bypassing the need for lengthy column select lines and main data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of DRAM cell arrays is increased, then the storage capacity is improved, but the total length of column select lines and main data lines increases, limiting the number of simultaneously accessible memory cells
Solution Approach 1:
The patent transitions from a two-dimensional planar architecture to a three-dimensional stacked architecture by placing the memory device and SoC on separate dies that are vertically stacked and bonded together. This dimensional change allows the column select lines and main data lines to be routed in the vertical dimension through TSVs, dramatically reducing the horizontal path length and enabling access to a larger number of memory cells simultaneously while maintaining high storage density.
2Area of stationary object
If the line widths of column select lines and main data lines are reduced to accommodate longer paths, then the space utilization is improved, but the number of first sense amplifiers that can be accessed at one time is limited
Solution Approach 1:
By moving the I/O interface to a separate SoC die and connecting through TSVs, the patent creates vertical interconnect paths that are independent of the horizontal line width constraints. This allows column select lines and main data lines to maintain sufficient width for high-speed operation while the three-dimensional stacking enables access to many more sense amplifiers simultaneously, dramatically increasing productivity without compromising space utilization.
3Ease of manufacture
If conventional two-dimensional DRAM architecture is used, then the manufacturing process is simpler, but the memory access speed and bandwidth are restricted due to long signal paths
Solution Approach 1:
The patent segments the memory system into two separate dies: a memory die containing the cell arrays and sense amplifiers, and an SoC die containing the I/O interface and control logic. This segmentation allows each die to be optimized independently for its specific function while the vertical bonding interface provides high-speed interconnection, achieving both manufacturing feasibility and high performance.
Solution Approach 2:
The transition to three-dimensional stacking with vertical TSV interconnects dramatically reduces signal path lengths compared to two-dimensional planar routing. The vertical pathways through the bonding interface provide direct, short connections between the memory cells and the I/O interface, enabling high-speed access and increased bandwidth while maintaining manufacturing practicality through established bonding and TSV technologies.
Data Source
AI summary
A method for accessing memory and a memory device using the same method are provided. The method includes: coupling, by a first sense amplifier (SA) of a memory, to a memory cell of the memory to receive data from the memory cell; coupling a first terminal of a transistor of the memory to the first SA; coupling a first command terminal of a system on chip (SoC) to a second terminal of the transistor, and coupling a first input/output (I/O) terminal of the SoC to a third terminal of the transistor; and issuing, by the SoC, an access command to the second terminal of the transistor to access the data output by the first SA through the third terminal of the transistor.