3D DRAM Structure Using HAR Holes and Selective SiGe Etching
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Solution Overview
Problem
Two-dimensional memory structures are reaching theoretical limits in density, and existing three-dimensional memory devices face challenges in scalability and processing, making it difficult to achieve memory densities comparable to two-dimensional DRAM without significant cost increases.
Innovation Solution
The use of alternating heteroepitaxy layers of crystalline silicon and silicon germanium, combined with selective etching processes, allows for the formation of three-dimensional dynamic random-access memory (3D DRAM) structures with scalable dimensions, featuring gate all-around transistors and precise control over feature sizes, enabling efficient construction of memory arrays with high density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional memory structures are used, then manufacturing process is simple, but memory density reaches theoretical limit
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertically stacked memory structures. This dimensional change allows multiple memory layers to be stacked above a single substrate area, dramatically increasing memory density without requiring proportional increases in substrate area, thereby resolving the contradiction between manufacturing simplicity and memory density.
2Quantity of substance
If three-dimensional memory structures are implemented, then memory density increases, but processing complexity and cost increase
Solution Approach 1:
The patent employs preliminary patterning actions where through-holes are formed first, followed by sequential deposition of alternating c-Si and c-SiGe layers. The selective etching of c-SiGe sacrificial layers is performed in advance to create voids that will later receive electrode materials. This preliminary structuring simplifies subsequent processing steps and reduces overall manufacturing complexity despite the three-dimensional architecture.
Solution Approach 2:
The memory structure is segmented into distinct functional layers: alternating c-Si active layers and c-SiGe sacrificial layers, with through-holes segmented into different regions for different purposes (capacitor formation, word line formation, bit line formation). This segmentation allows independent optimization and processing of each layer type, reducing overall processing complexity.
3Manufacturing precision
If alternating c-Si and c-SiGe layers are deposited, then selective etching capability is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent introduces local quality differentiation by using c-SiGe layers specifically as sacrificial materials in certain regions while maintaining c-Si layers as active memory elements in other regions. This local differentiation enables selective etching processes that remove only c-SiGe, creating precise three-dimensional structures with high manufacturing precision. The localized function assignment justifies the increased process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the production of 3D DRAM structures with densities beyond current capabilities, achieving approximately 1300 um² per megabit, reducing manufacturing costs and time while maintaining structural integrity and performance.
Implementation Method 1
depositing alternating layers of crystalline silicon (c-Si) material and crystalline silicon germanium (c-SiGe) material using an heteroepitaxy process onto a substrate
Implementation Method 2
etching of a pattern of holes with at least one high aspect ratio (HAR) hole into the substrate
Implementation Method 3
a liner of a first dielectric material which is removable by exposure to hydrogen fluoride (HF)
Data Source
AI summary
Methods for forming three-dimensional dynamic random-access memory (3D DRAM) structures that leverage a grid pattern of high aspect ratio holes to form subsequent features of the 3D DRAM. The method may include depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) using an heteroepitaxy process onto a substrate and HAR etching of a pattern of holes into the substrate. The holes configured to provide chemistry access to laterally etch or deposit materials to form 3D DRAM features without requiring subsequent HAR etching of holes to form the 3D DRAM features.