3D Capacitor-Less DRAM Structure Using Split Silicon Pillars
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher memory density due to the complexity and limitations of conventional capacitor structures in DRAM devices.
Innovation Solution
A manufacturing method for a semiconductor structure that involves forming a thin-film stacked structure on a substrate, creating a hole and growing an epitaxial silicon pillar, then etching to form a trench that divides the pillar into two halves, forming channel regions with specific doping types, and depositing gate dielectric and conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional capacitor structures are used in DRAM devices, then memory capacity can be achieved, but process complexity increases and memory density is limited
Solution Approach 1:
The patent removes the capacitor structure from the traditional 1T1C DRAM architecture, extracting the energy storage function and replacing it with a capacitor-less memory cell design that uses a single transistor with specific doping configurations to achieve both storage and readout functions, thereby reducing structural complexity while maintaining memory functionality
Solution Approach 2:
The patent creates a memory structure where a single transistor performs multiple functions previously requiring separate components (storage and readout), enabling the same structure to serve as both memory element and readout mechanism, thus improving memory density without proportionally increasing device complexity
2Quantity of substance
If process dimensions are miniaturized to increase memory capacity, then memory density improves, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent divides the semiconductor structure into distinct doped regions (first doped region, second doped region, third doped region) with different doping types and concentrations, allowing each region to be optimized independently for its specific function while maintaining overall device performance at miniaturized dimensions
Solution Approach 2:
The patent implements spatially varying doping concentrations and types within the memory structure, with high-concentration doped regions for stability, low-concentration regions for channel control, and specifically doped areas for readout functionality, enabling precise local optimization that maintains manufacturing feasibility at small dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the process by eliminating the need for capacitor structures, enabling easier realization of higher memory density in 3D NOP capacitor-less DRAM devices.
Implementation Method 1
growing an epitaxial silicon pillar in the first hole
Implementation Method 2
forming a first channel region of a first doping type in a sidewall of the first half pillar away from the first trench, and forming a second channel region of a second doping type in a sidewall of the second half pillar away from the first trench
Data Source
AI summary
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: depositing a thin-film stacked structure on a substrate; forming a first hole in the thin-film stacked structure; growing an epitaxial silicon pillar in the first hole; etching the thin-film stacked structure and the epitaxial silicon pillar along a first direction to form a first trench, the first trench passing through a center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half pillar and a second half pillar; forming a first isolation layer; forming a first channel region of a first doping type, and forming a second channel region of a second doping type; and forming a gate dielectric layer and a gate conductive layer on a surface of each of the first channel region and the second channel region.