3D DRAM Stacked Semiconductor Doping With Split Implant Energies
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Solution Overview
Problem
The 3D DRAM semiconductor structure faces challenges in achieving uniform ion doping due to its stacked structure, leading to non-uniform doped ion concentration distribution, which affects the refresh time and reliability of the device.
Innovation Solution
A method involving the formation of stacked structures with sacrificial layers and semiconductor layers, where ion implantation is performed at different energies to maintain doped ion concentrations within a preset range in the bit line and capacitive regions, improving doping control capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ion doping process is used in 3D DRAM stacked structure, then memory cells can be stacked on top of logic cells to achieve higher yield per unit wafer area, but the doping control capability is reduced resulting in non-uniform concentration distribution of doped ions
Solution Approach 1:
The patent divides the doping process into multiple stages with different ion implantation energies. Different energy levels are used for different depth ranges, allowing precise control of dopant distribution in each layer of the stacked structure. This segmentation of the doping process resolves the contradiction by enabling both high productivity through stacking and precise doping control in each layer.
Solution Approach 2:
The patent applies different ion implantation energies to achieve different dopant concentration profiles at different depths. By tailoring the doping conditions locally for each layer, the method maintains uniform concentration distribution in each semiconductor layer while enabling the stacked structure for higher productivity.
2Device complexity
If ion implantation is performed on stacked semiconductor layers, then 3D DRAM structure can be formed, but the concentration distribution of doped ions becomes non-uniform affecting refresh time
Solution Approach 1:
The patent employs dynamic adjustment of ion implantation energy during the doping process. By varying the energy levels in different doping steps, the method adapts to the specific requirements of each layer in the stacked structure, ensuring uniform dopant concentration and reliable refresh time performance.
Solution Approach 2:
The patent changes the ion implantation energy parameter to control dopant distribution. By adjusting the energy parameter across different implantation steps, uniform concentration distribution is achieved in each layer of the stacked structure, thereby maintaining reliability and consistent refresh time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform doped ion distribution, enhancing the reliability and performance of the semiconductor device by maintaining ion concentrations within specific ranges in the bit line and capacitive regions.
Implementation Method 1
performing an ion implantation on the first semiconductor layer and the second semiconductor layer, wherein an energy at which the ion implantation is performed on the first semiconductor layer is greater than an energy at which the ion implantation is performed on the second semiconductor layer
Data Source
AI summary
Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The method includes: providing a substrate, wherein the substrate includes a word line region, a bit line region, and a capacitive region arranged adjacently; forming a first stacked structure that covers a surface of the substrate, wherein the first stacked structure includes a first sacrificial layer located on the surface of the substrate and a first semiconductor layer located on a surface of the first sacrificial layer; forming a second stacked structure that covers a surface of the first stacked structure, wherein the second stacked structure includes a second sacrificial layer located on the surface of the first stacked structure and a second semiconductor layer located on a surface of the second sacrificial layer; and performing an ion implantation on the first semiconductor layer and the second semiconductor layer.