3D DRAM Cell Layout With Stacked Storage Nodes and Low Contact Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As design rules shrink, there is a challenge in reducing the lateral footprint of memory cells in DRAM arrays to increase memory array density while maintaining effective charge storage and reducing contact resistance, especially with limited semiconductor space.
Innovation Solution
The implementation of a three-dimensional memory architecture with horizontally oriented access devices and storage nodes, where storage nodes are vertically stacked between access devices, reducing the lateral footprint and improving charge storage capacity, and utilizing gate all around structures and specific electrode configurations to enhance contact resistance and material compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If design rules are shrunk to increase memory array density, then memory array density is improved, but contact resistance increases
Solution Approach 1:
The patent transitions from planar memory cell layout to three-dimensional vertically stacked architecture. Storage nodes are positioned at different vertical levels (first level and second level) above the substrate, with access devices connecting these vertically separated nodes. This dimensional change allows increased memory density without proportionally increasing contact resistance, as the vertical stacking enables more efficient use of the contact area between access devices and storage nodes.
2Quantity of substance
If vertically stacked storage nodes are implemented, then memory array density is improved, but device complexity increases
Solution Approach 1:
The memory array is segmented into multiple vertical levels with storage nodes positioned at different heights (first level and second level). Access devices are distributed across these levels, with each access device connected to storage nodes at its level. This segmentation into modular vertical units increases density while maintaining manageable complexity through repetitive structural patterns.
Solution Approach 2:
The access devices serve multiple functions: they act as selection transistors for memory cells and simultaneously provide conductive pathways between different vertical levels. The vertically stacked architecture allows the same structural pattern to be repeated across multiple levels, reducing overall device complexity through universality of design elements.
Data Source
AI summary
Systems, methods and apparatus are provided for an array of vertically stacked memory cells. The vertically stacked memory cells have horizontally oriented access devices having a first source/drain region, a channel region, and a second source drain and horizontally oriented storage nodes that are vertically separated from the access devices. Horizontally oriented access lines are coupled to gates, separated from the respective channel regions by gate dielectrics, and vertically oriented digit lines are coupled to respective first source/drain regions. The horizontally oriented storage nodes each have a first electrode coupled to the second source/drain regions of the access devices and each first electrode opposes two different sides of the horizontal access devices including an electrical contact with a vertical side of the second source/drain regions.