3D DRAM Memory Structure With Vertical Tunnel Diodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DRAMs face challenges in miniaturization due to complex processes and increasing capacitor aspect ratios, necessitating a new dynamic random access memory structure.
Innovation Solution
A 3D DRAM structure with a plurality of insulating and gate layers, doping layers, and a columnar channel, forming 1D1T memory cells with high-density tunnel diodes and read transistors, allowing for simplified manufacturing and reduced size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional DRAM structure (1T1C) is used, then data storage function is achieved, but device size cannot be easily miniaturized and capacitor aspect ratio increases dramatically
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a 3D vertical stack architecture. Multiple insulating layers and gate layers are stacked vertically to form three-dimensional tunnel diodes and read transistors, enabling high-density memory cells by utilizing the vertical dimension for miniaturization while maintaining manufacturability
Solution Approach 2:
The patent implements nested structures where gate layers are wrapped around columnar channels, and insulating layers are positioned between doping layers to form integrated three-dimensional components. The gate layers surround the columnar channel in a nested configuration, creating compact vertical transistors and diodes that reduce overall device footprint
2Ease of manufacture
If conventional DRAM manufacturing process is used, then manufacturing capability is maintained, but process complexity increases and costs rise
Solution Approach 1:
The manufacturing process is divided into sequential stages: forming alternating insulating and gate layers, creating holes through the stack, depositing doping layers in specific sequences, and forming columnar channels. This segmented approach allows each layer and doping step to be processed independently using standard semiconductor fabrication techniques, maintaining ease of manufacture while achieving complex three-dimensional structures
Solution Approach 2:
The patent forms the complete stack of insulating and gate layers before creating the holes and doping structures. The alternating layers are prepared in advance, providing a pre-configured template that guides subsequent hole formation and doping operations, thereby simplifying the overall manufacturing process and improving productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure enables high-density memory cells and arrays with reduced manufacturing costs, enhancing scalability and performance.
Implementation Method 1
The first doping layer and the second doping layers form a plurality of tunnel diodes
Data Source
AI summary
A memory structure includes insulating layers, gate layers, a first doping layer, second doping layers, third doping layers, a columnar channel, a first dielectric layer, second dielectric layers, and a third dielectric layer. The first doping layer and the columnar channel penetrate through the insulating layers and the gate layers that are alternately stacked. The second doping layers are in direct contact with the first doping layer to form tunnel diodes, in which the second doping layers and the insulating layers are alternately stacked. The third doping layers surround the columnar channel and are connected to the second doping layers. The first dielectric layer is between the first doping layer and the gate layers. The second dielectric layers are between the third doping layers and the gate layers. The third dielectric layer is between the columnar channel and the third doping layers.