3D DRAM Cell Layout With Vertical Storage Nodes and G2S Access
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Solution Overview
Problem
As design rules shrink, there is a challenge in reducing the lateral footprint of memory cells in DRAM arrays to increase memory array density while maintaining effective charge storage and reducing contact resistance, especially when using materials with lower mobility.
Innovation Solution
A three-dimensional memory design with vertically stacked storage nodes and horizontally oriented access devices, where storage nodes are fabricated vertically between access devices to reduce the lateral footprint, and the access devices have gates opposing each side of the channel regions to form gate on two side (G2S) structures, improving charge storage and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If storage nodes are fabricated vertically between access devices, then memory array density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar memory cell layout to three-dimensional vertical stacking, where storage nodes are positioned vertically between access devices. This dimensional change increases memory density by utilizing the vertical space rather than only lateral expansion, allowing multiple storage nodes to be stacked above and below access devices in the same lateral footprint.
Solution Approach 2:
The memory structure is segmented into distinct functional layers: access devices in intermediate layers and storage nodes in separate upper and lower layers. This segmentation allows independent optimization of each component and simplifies the manufacturing process by enabling separate formation steps for access devices and storage nodes, reducing overall manufacturing complexity despite the three-dimensional architecture.
2Reliability
If access devices have gates opposing each side of the channel regions to form G2S structures, then charge storage is improved, but device complexity increases
Solution Approach 1:
The Gate-on-Two-Sides structure provides localized control of the channel region from two opposite directions, creating non-uniform electric field distribution that enhances charge storage capability. This local quality improvement targets specific regions where charge accumulation is needed, allowing better control over threshold voltage and charge retention without requiring complete structural redesign of the entire device.
3Area of stationary object
If vertically stacked storage nodes are used, then lateral footprint is reduced, but contact resistance increases
Solution Approach 1:
The patent moves the contact interface from a lateral planar connection to a vertical through-contact architecture. Vertical access lines extend through multiple layers to establish electrical connections with storage nodes, distributing the contact interface across the vertical dimension. This reduces the lateral footprint of individual contacts while maintaining adequate contact area through the vertical extension, thereby reducing overall lateral footprint without significantly increasing contact resistance.
Data Source
AI summary
Systems, methods and apparatus are provided for an array of vertically stacked memory cells. The vertically stacked memory cells have horizontally oriented access devices having a first source/drain region, a channel region, and a second source drain and horizontally oriented storage nodes that are vertically separated from the access devices. Vertically oriented gates are separated from the respective channel regions by gate dielectrics, and horizontally oriented digit lines are coupled to respective first source/drain regions. The horizontally oriented storage nodes each have a first electrode coupled to the second source/drain regions of the access devices and each first electrode opposes two different sides of the horizontal access devices including an electrical contact with a vertical side of the second source/drain regions.