3D DRAM Film Stack Composition for Wafer Bowing Reduction
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Solution Overview
Problem
Increasing the number of layers in 3D DRAM devices beyond the 10 nm node leads to wafer bowing due to lattice mismatch-induced stress, which prevents accurate lithography and increases process complexity and costs, as current stress-relieving methods only partially alleviate the issue.
Innovation Solution
Forming 3D DRAM devices using a 3-color process with film stacks comprising doped SiGe and silicon layers, where the first doped SiGe layer has an empirical formula Si1-xGex and the second doped SiGe layer has an empirical formula Si1-yGey, with different doping amounts or Si:Ge ratios, and a doped silicon layer, resulting in etch selectivity greater than 200:1 with halide-based etchants, thereby reducing wafer bowing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers is increased beyond the 10 nm node to scale density, then bit density is improved, but wafer bowing increases due to lattice mismatch-induced stress
Solution Approach 1:
The patent changes the material composition parameters by introducing doped SiGe layers with specific doping concentrations (0.5-2.5% carbon or boron) and varying Si:Ge ratios between layers. This parameter modification allows control of lattice mismatch and stress distribution, enabling higher layer counts (100+ stacks) without excessive wafer bowing while maintaining etch selectivity greater than 200:1
Solution Approach 2:
The patent uses composite material structures with alternating doped SiGe layers and doped silicon layers. The doped SiGe layers serve as sacrificial layers with different mechanical and etching properties compared to the silicon channel layers. This composite approach enables selective removal of sacrificial layers while maintaining structural integrity and controlling stress-induced wafer bowing during the formation of high-density 3D DRAM devices
2Shape
If conventional layer stacks are engineered to reduce wafer bowing, then wafer bowing is decreased, but etch selectivity decreases
Solution Approach 1:
The patent applies local quality by doping specific SiGe layers with carbon or boron at controlled concentrations (0.5-2.5%) to create localized regions with enhanced etch selectivity. The doping is applied selectively to sacrificial layers rather than uniformly across all layers, enabling differential etching behavior where doped SiGe layers are removed faster than silicon channel layers (etch selectivity > 200:1) while the doped regions also provide stress control to reduce wafer bowing
3Shape
If additional stress-relieving films are deposited at the back side of the wafer, then wafer bowing is partially alleviated, but process complexity and costs increase
Solution Approach 1:
The patent extracts the stress management function from separate back-side stress-relieving films and integrates it directly into the front-side layer stack structure. By incorporating doped SiGe sacrificial layers with controlled stress properties within the main device stack, the patent eliminates the need for additional back-side films, reducing process complexity while maintaining effective stress control and wafer flatness during fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3-color process effectively reduces wafer bowing and improves etch selectivity, allowing for accurate lithography and simplified process steps, enabling the formation of high-density 3D DRAM devices with reduced bowing and increased layer stacks without the need for additional stress-relieving films.
Implementation Method 1
One or more of the first doped SiGe layers or second doped SiGe layers are selectively etched from all of the film stacks through the channel
Implementation Method 2
epitaxially growing a multi-layer stack comprising an epitaxial silicon channel layer and two or more sacrificial epitaxial layers
Data Source
AI summary
Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.