3D DRAM Window Centering for Balanced LDL Sensing
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Solution Overview
Problem
In three-dimensional dynamic random-access memory (3D DRAM) devices, there is a mismatch in capacitance between data and reference local digit lines (LDLs), leading to an unbalanced sensing window during read operations, which affects data retention and accuracy.
Innovation Solution
A window centering scheme is implemented by adjusting the voltage on the reference LDL using a switch to center the sensing window between the voltage for a zero and a one, compensating for capacitance mismatches through the use of bleeder supply circuits and multiplexers to optimize data retention and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference LDL is used for sensing operations, then data read accuracy can be improved, but capacitance mismatch between data and reference LDLs causes the sensing window to become unbalanced
Solution Approach 1:
The patent changes the voltage parameter of the reference LDL by applying a reference voltage through a switch and bleeder supply circuit. This voltage adjustment compensates for capacitance mismatch between data and reference LDLs, centering the sensing window and simultaneously improving both sensing balance and data retention reliability
Solution Approach 2:
The patent introduces a bleeder supply circuit and switch as intermediary components between the voltage source and the reference LDL. These intermediaries enable precise voltage control and adjustment, allowing the reference LDL voltage to be optimized for both sensing accuracy and data retention without directly modifying the LDL structure
2Reliability
If the idle bias on LDLs is optimized for data retention, then the margin between ones and zeros retention improves, but the sensing window becomes unbalanced
Solution Approach 1:
The patent independently adjusts the voltage parameter of the reference LDL using a bleeder supply circuit and switch. This allows optimization of the sensing window balance without affecting the idle bias settings that determine data retention margin, resolving the trade-off between these two performance metrics
Solution Approach 2:
The patent segments the voltage control functions by separating the idle bias control (for data retention) from the reference LDL voltage control (for sensing window balance). This segmentation is achieved through dedicated circuits: one for maintaining idle bias and another with switch and bleeder supply for reference voltage adjustment, allowing independent optimization of both functions
Data Source
AI summary
A variety of applications can include an apparatus having a three-dimensional (3D) memory device with a mechanism for window centering for zeros and ones sensing. A 3D memory device can be constructed to implement a window centering scheme to add charge to the reference side of a sense amplifier such that a process window is centered between a voltage for a zero and a voltage for a one on a reference side of the sense amplifier. A 3D DRAM device can be constructed to selectively apply an idle bias to a local digit line, where the idle bias has a voltage in a range to optimize data retention or a reference voltage to the local digit line to bias the local digit line to a centering voltage.