3D Dual-Port Bit Cell Vertical Stacking
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Solution Overview
Problem
Conventional multi-port SRAM structures face challenges with increased area occupation and signal routing complexities due to wider word line directions, leading to higher capacitive loading and aspect ratio impacts, especially in heavy input/output designs.
Innovation Solution
A three-dimensional dual-port bit cell design where one set of port elements is disposed on a first layer and another set on a vertically adjacent layer, reducing footprint area and parasitic resistance and capacitance, thereby improving overall performance and simplifying signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional multi-port SRAM structures use word lines in different metal lines, then multiple reads or writes can occur simultaneously, but capacitive loading increases due to different metal lengths
Solution Approach 1:
The patent transitions from planar routing to three-dimensional vertical stacking, moving word lines from different metal lines to different physical layers. This dimensional change allows simultaneous multi-port operations while equalizing word line lengths, thereby reducing capacitive loading variations and energy loss.
2Productivity
If conventional multi-port SRAM structures use wider word line directions, then multiple ports can operate simultaneously, but the aspect ratio of the SRAM array is impacted
Solution Approach 1:
The invention resolves aspect ratio distortion by transitioning from horizontal expansion to vertical stacking. Multiple word lines are routed through different layers rather than extending horizontally, maintaining a compact rectangular footprint and preserving the desired aspect ratio while enabling multi-port operations.
3Productivity
If conventional multi-port SRAM structures use wider word line directions, then multiple ports can operate simultaneously, but signal routing complexities increase
Solution Approach 1:
The patent simplifies signal routing by utilizing the vertical dimension for interconnect layers. Word lines and bit lines are routed in separate physical layers, eliminating the need for complex planar routing and reducing signal interference, thereby decreasing device complexity while maintaining multi-port functionality.
4Productivity
If conventional multi-port SRAM structures are designed with wider input/output, then data throughput increases, but the periphery logic circuitry is doubled compared to single-port SRAM
Solution Approach 1:
The patent merges read and write operations into a unified three-dimensional architecture. By stacking word lines and bit lines vertically, the periphery logic circuitry serves multiple ports simultaneously, reducing the total area required compared to conventional multi-port designs that duplicate logic circuits for each port.
Data Source
AI summary
A three-port, three-dimensional bit cell generally comprises a read portion of a cell disposed on a first tier. The read portion comprises a plurality of read port elements. The three-port bit cell further comprises a write portion of the cell disposed on a second tier that is vertically stacked with respect to the first tier. The first and second tiers are coupled using at least one via. The write portion comprises a plurality of write port elements.