3D Electronic System Vertical Contact Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for three-dimensional integration of electronic systems face challenges in achieving high packing density and switching speeds due to limitations in the formation of vertical contacts, particularly when these contacts are formed after Front-End-Of-Line (FEOL) processes, requiring compatibility with Back-End-Of-Line (BEOL) processes and involving thick dielectric layers.
Innovation Solution
A method involving the formation of vertical contacts on a second substrate with an epitaxial layer, where the substrate material is thinned to expose the contacts, allowing for a three-dimensional integration by aligning and connecting the contacts with pre-processed components on a first substrate, using conductive materials like copper or tin for stable electrical and mechanical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If vertical contacts are formed after complete processing of components or component substrates, then there is no intervention in the technology of component production, but the packing density and switching speeds cannot be further increased
Solution Approach 1:
The patent applies preliminary action by forming vertical contacts (through-silicon vias) during the FEOL processes before BEOL metallization, rather than after complete processing. This allows the vertical contact structure to be prepared in advance, enabling subsequent integration steps to proceed more efficiently and achieve higher packing densities without interfering with component production technology
Solution Approach 2:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by forming through-silicon vias that extend vertically through the substrate. This dimensional change enables stacking of multiple device layers, significantly increasing packing density and allowing independent selection of vertical contact positions to optimize switching speeds
2Productivity
If vertical contacts are produced as part of component fabrication after FEOL but before BEOL, then packing density and switching speeds can be increased, but full compatibility with BEOL processes is required
Solution Approach 1:
The patent changes the timing parameter of vertical contact formation to occur during FEOL processes rather than after complete processing. This parameter change allows the vertical contact structure to be established before BEOL metallization begins, enabling higher packing densities while managing compatibility requirements through careful process sequencing
Solution Approach 2:
The patent segments the integration process into distinct phases: FEOL processes for forming vertical contacts and active devices, followed by BEOL processes for metallization and interconnection. This segmentation allows independent optimization of each phase, enabling high packing density through vertical contact formation while maintaining compatibility with standard BEOL process flows
3Ease of manufacture
If conventional methods are used with thick dielectric layers separating metal layers, then process compatibility is maintained, but the formation of vertical contacts is constrained
Solution Approach 1:
The patent moves from two-dimensional planar contact formation constrained by thick dielectric layers to three-dimensional vertical contact formation through the substrate. This dimensional change provides freedom to position vertical contacts independently of dielectric layer thickness, enabling versatile contact placement while maintaining process compatibility through standardized FEOL and BEOL process sequences
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher packing density and switching speeds by allowing for flexible positioning of vertical vias and reducing the need for thick dielectric layers, while maintaining compatibility with existing processing technologies.
Implementation Method 1
a semiconductor layer (or epitaxial layer) is formed on the main side of the second substrate
Data Source
Figure 1~(1B)
Figure 2~(2C)
Figure (2D)~(2E)
AI summary
A method for manufacturing a three-dimensional electronic system comprises: provision of a first integrated circuit structure in a first substrate (110), wherein the first integrated circuit structure has a contact face (150) on a first main side (117) of the first substrate (110); provision of a second substrate (210) having a main side (215); formation of a vertical contact region (240) in the second substrate (210). Next, the method comprises formation of a semiconductor layer (212) on the main side (215) of the second substrate (210); formation of a semiconductor component of a second integrated circuit structure in the second substrate (210) with the semiconductor layer (212); removal of substrate material from a side (217) of the second substrate (210) that is opposite the main side (215), so that the vertical contact region (240) is electrically exposed on the opposite side (217); arrangement of the first and second substrates (110, 210) on one another so as to orient the vertical contact region (240) to the contact face (150), so that electrical connection is set up between the first and second integrated circuit structures via the vertical contact region (240) and the contact face (150).