3D Express Link Architecture for NoC Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 2D mesh network-on-chip (NoC) designs suffer from latency and congestion issues due to high average data-hop counts and hotspots, which hinder performance, bandwidth, and power, performance, and area (PPA) targets.
Innovation Solution
The implementation of a multi-dimensional (3D) express link architecture that extends the topology of a first die using the metal layers of a second die, adding express links to a 2D mesh to couple non-neighbor router logic through a multi-layered structure, thereby reducing latency and increasing bisection bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 2D mesh topology is used for scalable processors, then the design can be tiled and replicated for given PPA targets, but latency increases due to paths crossing significant number of routers
Solution Approach 1:
The patent introduces a third dimension to the traditional 2D mesh network by adding vertical routing paths through multiple layers. This allows data to travel through the Z-axis (up/down between layers) rather than being constrained to horizontal paths, significantly reducing the number of routers data packets must traverse and thereby reducing latency while maintaining scalability.
Solution Approach 2:
The network is segmented into multiple layers with dedicated routing paths for different traffic types. By dividing the network into hierarchical levels (core routers in one layer, edge routers in another), the patent creates specialized pathways that reduce congestion and improve overall bandwidth while maintaining manageable complexity.
2Adaptability or versatility
If 2D mesh topology is used, then tiled design can be replicated, but congestion occurs in the middle of the mesh structure
Solution Approach 1:
By adding vertical routing paths through multiple layers, the patent distributes traffic across three dimensions rather than concentrating it in the center of a 2D mesh. This dimensional expansion provides alternative pathways around congestion points, maintaining high bandwidth utilization while preserving the scalable tiled architecture.
Solution Approach 2:
The patent introduces intermediate routing layers that act as mediators between edge routers and core routers. These intermediate structures provide alternative pathways that bypass congested regions, allowing data to route around bottlenecks while maintaining the overall mesh topology and its scalability benefits.
3Quantity of substance
If more routers are added to increase logic and wires for computation, then storage and communication capacity increases, but path length and latency increase
Solution Approach 1:
The patent resolves this contradiction by organizing routers in a three-dimensional spatial arrangement where vertical shortcuts provide direct pathways between distant nodes. This allows the network to scale in logic capacity by adding more routers while maintaining low latency through the Z-axis routing paths that bypass the need to traverse through intermediate routers in the X-Y plane.
Data Source
AI summary
Various implementations described herein refer to a device having a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first network that links nodes together in the first layer. The device may have a second network that links the nodes in the first layer together by way of the second layer so as to reduce latency related to data transfer between the nodes.