3D Fan-Out Packaging Structure for Compact High-Density Chip Integration
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Solution Overview
Problem
Current fan-out packaging technologies face challenges with large package size, high cost, complex procedures, and low reliability, which hinder the integration of high-density chips for 5G and AI applications, requiring a more efficient and compact packaging solution.
Innovation Solution
A wafer system-level three-dimensional fan-out packaging structure is developed, involving a carrier substrate with a redistribution layer, conductive connecting posts, patch elements, and solder bumps, where the redistribution layer is formed with dielectric and metal layers, and the structure is cut to create package structures that are then bonded to achieve double-sided packaging, enhancing integration and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If through-silicon-via (TSV) technology or silicon interposers are used for high-density integrated multi-chip packaging, then ultra-small pins can be led out and connected effectively, but manufacturing cost increases significantly
Solution Approach 1:
The patent replaces expensive TSV and silicon interposer technologies with a cost-effective fan-out packaging approach using organic substrates and simplified interconnection structures. The design uses standard PCB fabrication processes and common packaging materials to achieve ultra-fine pitch connections without the high manufacturing costs of TSV or silicon interposers
Solution Approach 2:
The patent changes the packaging architecture from vertical TSV interconnections to horizontal fan-out interconnections on an organic substrate. This parameter change in the interconnection topology enables ultra-small pin spacing to be achieved through planar routing rather than through-silicon vias, significantly reducing manufacturing cost while maintaining precision
2Adaptability or versatility
If existing fan-out packaging technologies are used, then wafer reconstruction and rewiring can be achieved, but package area and thickness increase due to limited wiring precision
Solution Approach 1:
The patent transitions from two-dimensional planar packaging to three-dimensional stacked packaging with multiple organic substrates layered vertically. This dimensional change enables high-density integration by utilizing the vertical dimension for stacking multiple chips and interconnection layers, thereby reducing the horizontal package area while maintaining rewiring capabilities through vertical vias and inter-layer connections
3Adaptability or versatility
If package components and functions are increased to meet demand, then system functionality improves, but package volume increases occupying more area and vertical space
Solution Approach 1:
The patent implements a nested packaging structure where multiple chips and functional components are stacked vertically within a compact volume. The organic substrates are layered like nested dolls, with each layer containing chips, interconnection layers, and passive components. This nested arrangement enables increased package functionality and component density while minimizing the overall package volume by utilizing vertical stacking rather than horizontal expansion
Data Source
AI summary
A wafer system-level three-dimensional fan-out packaging structure and a manufacturing method therefor. The method includes: forming a redistribution layer, where the redistribution layer includes a first surface and a second surface opposite to each other; forming a conductive connecting post on the second surface of the redistribution layer; bonding the patch element to the second surface of the redistribution layer; forming a plastic packaging layer on the second surface of the redistribution layer; thinning the plastic packaging layer; forming a plurality of solder bumps on a side of the plastic packaging layer that faces away from the redistribution layer; cutting the redistribution layer and the plastic packaging layer to obtain a number of first package structures; and bonding a second package layer to the first surface of the redistribution layer of one of the first package structures.