3D Fan-Out Package Structure With Dielectric Encapsulation
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the size of electronic components and packaging, requiring smaller, more integrated packages that minimize area usage while maintaining efficient encapsulation and connectivity without introducing imperfections or increasing process complexity.
Innovation Solution
A 3D integrated fan-out package structure is formed using a carrier substrate with adhesive layers, dielectric materials, and conductive patterns, where dies are encapsulated in dielectric material rather than molding compounds, and through-package vias are formed to reduce steps and enhance throughput, allowing for efficient packaging without grinding-induced imperfections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If molding compounds are used to encapsulate dies, then encapsulation is achieved, but surface imperfections and grinding-induced defects are introduced
Solution Approach 1:
The patent extracts the problematic molding compound encapsulation step and replaces it with dielectric material lamination. This removes the source of surface imperfections and grinding-induced defects while maintaining the essential encapsulation function through alternative means (dielectric layers formed by lamination processes).
Solution Approach 2:
The invention changes the material parameter from molding compound to dielectric material, and changes the process parameter from molding and grinding to lamination. This parameter transformation eliminates the harmful effects of molding compound encapsulation while achieving the desired encapsulation result with superior surface quality.
2Reliability
If traditional packaging processes are used, then encapsulation is achieved, but process complexity increases
Solution Approach 1:
The patent merges the encapsulation function with the dielectric layer formation process. Instead of separate molding and grinding steps, the dielectric material lamination simultaneously provides both electrical isolation and physical encapsulation, reducing process complexity while maintaining reliability.
Solution Approach 2:
The dielectric material layers serve multiple functions: they provide electrical insulation, mechanical encapsulation, and surface planarization. This multi-functionality eliminates the need for separate dedicated encapsulation steps, thereby reducing overall process complexity while achieving reliable encapsulation.
3Area of stationary object
If smaller packages are designed, then area usage is reduced, but integration density requirements increase
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional vertical stacking with through-package vias. This dimensional change allows multiple dies to be interconnected vertically, enabling high integration density within a reduced footprint area by utilizing the vertical dimension for signal routing and component interconnection.
Solution Approach 2:
The invention implements a nested structure where multiple dies are stacked vertically and interconnected through through-package vias. This nesting approach allows compact arrangement of multiple functional blocks within a small area, achieving high integration density while maintaining individual die functionality and enabling efficient area utilization.
Data Source
AI summary
An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.