3D Fan-Out Memory Packaging Without TSVs or Multi-Layer Substrates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional semiconductor packaging technologies face limitations in supporting high integration levels and increasing costs due to the need for multiple substrate layers and large line widths/spacings, which are not compatible with advanced integrated circuit manufacturing requirements.
Innovation Solution
A three-dimensional fan-out memory package structure using a fan-out pattern with metal connection pillars and rewiring layers to connect memory and peripheral circuit chips without through-silicon-via holes, reducing line width/spacing to 1.5 µm/1.5 µm and eliminating the need for a circuit substrate, enabling high-density and high-integration packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional substrate manufacturing with multiple substrate layers is used to support more chip I/Os, then the electrical connection capability is improved, but the overall cost increases and the manufacturing process becomes more complex
Solution Approach 1:
The patent transitions from traditional two-dimensional substrate routing to three-dimensional vertical interconnection through metal connection pillars. Multiple memory chips are stacked vertically with bonding pads on step surfaces, and electrical connections are established through vertical metal pillars rather than horizontal substrate traces, enabling high-density I/O support without increasing substrate layer complexity
Solution Approach 2:
The patent combines multiple functions into the substrate: it serves as both the mounting platform for memory chips and the interconnection medium through integrated metal connection pillars. The substrate integrates the functions of mechanical support, electrical interconnection, and signal routing, eliminating the need for separate complex multi-layer substrate structures
2Ease of manufacture
If traditional substrate manufacturing with large line width/line spacing (20 µm/20 µm or 50 µm/50 µm) is used, then the manufacturing process is simpler, but it cannot support the high integration requirements of advanced front-end chip manufacturing
Solution Approach 1:
The patent replaces traditional planar substrate trace routing with vertical metal connection pillars and fan-out rewiring layers. This substitution enables much finer line width and spacing (1.5 µm/1.5 µm) to be achieved, matching advanced front-end manufacturing capabilities while maintaining ease of manufacture through standardized pillar formation processes
Solution Approach 2:
The patent dramatically reduces the characteristic dimensions of interconnect features from traditional 20 µm or 50 µm line widths to 1.5 µm line widths in the rewiring layers. This parameter change enables the substrate to support high integration levels compatible with advanced front-end chip manufacturing while maintaining manufacturing feasibility
3Adaptability or versatility
If advanced packaging technologies such as 2.5D fan-out wafer level packaging, BGA, CSP, or WLP are used to support high integration, then the packaging capability is improved, but the manufacturing cost increases and the manufacturing time is longer
Solution Approach 1:
The patent segments the packaging process into distinct functional layers: memory chip stacking with stepped configuration, metal connection pillar formation for vertical interconnection, encapsulation layer formation for protection, and fan-out rewiring layer formation for signal routing. This segmentation enables each layer to be optimized independently while maintaining overall process efficiency and high packaging capability
Solution Approach 2:
The patent employs three-dimensional stacking of memory chips with vertical metal connection pillars for inter-chip connections, eliminating the need for complex lateral routing required in traditional 2D packaging. This vertical integration approach achieves high packaging density and advanced packaging capability while simplifying the manufacturing process and reducing production time
Data Source
AI summary
A three-dimensional fan-out memory package structure and a packaging method are disclosed. The package structure includes a three-dimensional fan-out memory package unit, which includes: a memory chip stack having at least two memory chips laminated in a stepped configuration, each memory chip is provided with a bonding pad; first metal connection pillars formed on the bonding pads; second metal connection pillars; a first encapsulating layer; a first rewiring layer formed on a back side of the memory chip stack; a second rewiring layer formed over a front side of the memory chip stack; and metal bumps. The package structure further includes: at least one peripheral circuit chip electrically connected with the first rewiring layer; and a second encapsulating layer, which encapsulates the peripheral circuit chip. The package structure allows for high-density and high-integration of line width/line spacing. The process time can be shortened, and the efficiency is high.