3D Fan-Out Memory POP Structure for High-Density Packaging
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Solution Overview
Problem
Traditional substrate manufacturing techniques are limited in supporting high integration levels of chip manufacturing, leading to increased costs and complexity due to the need for multiple layers and large line widths/spacings, which are not sufficient for advanced packaging requirements.
Innovation Solution
A package-on-package (POP) structure is developed, featuring a three-dimensional fan-out memory device and a two-dimensional fan-out peripheral circuit, interconnected through multiple rewiring layers, eliminating the need for through-silicon-via holes and reducing line width/spacing to 1.5 μm/1.5 μm, enabling high-density and high-integration packaging with reduced thickness and process time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional substrate manufacturing techniques are used to support high integration levels, then the number of substrate layers increases, but the manufacturing cost and complexity increase significantly
Solution Approach 1:
The patent transitions from traditional two-dimensional substrate layer stacking to a three-dimensional fan-out wafer-level packaging structure. Multiple memory chips are stacked vertically with rewiring layers interconnecting them, achieving high integration by utilizing the third dimension (vertical stacking) rather than adding more horizontal substrate layers. This dimensional change allows dense interconnection without proportionally increasing substrate layer count.
Solution Approach 2:
The patent employs a nested structure where multiple memory chips are stacked and enclosed within a single package unit, with rewiring layers nested between the chips. The first package unit containing stacked memory chips is then integrated with a second package unit containing peripheral circuits, creating a package-on-package nested architecture. This nesting achieves high integration within compact structural boundaries.
2Quantity of substance
If more chip I/O connections are placed on substrates, then the number of substrate layers increases, but the manufacturing cost increases
Solution Approach 1:
The patent achieves increased I/O connections by utilizing vertical stacking of memory chips with rewiring layers in between, rather than adding more horizontal substrate layers. The fan-out structure allows I/O pads to be redistributed across multiple layers, increasing connection capacity without linearly increasing substrate layer count and associated manufacturing costs.
Solution Approach 2:
The patent uses identical memory chips stacked multiple times to create multiple I/O connections. Each memory chip in the stack provides the same functional interface, and the rewiring layers replicate connection patterns across layers. This copying approach increases total I/O capacity without requiring custom-designed substrate layers for each connection, reducing manufacturing complexity and cost.
3Quantity of substance
If the line width and spacing are reduced to achieve higher integration, then the manufacturing precision requirements increase
Solution Approach 1:
The patent achieves high integration density by stacking memory chips vertically with rewiring layers, utilizing the vertical dimension rather than reducing horizontal line width and spacing. The fan-out structure distributes I/O connections across multiple vertical layers, allowing larger pad dimensions and relaxed manufacturing precision requirements compared to planar high-density designs.
Solution Approach 2:
The patent changes the geometric parameters of the packaging structure by transitioning from a planar layout to a three-dimensional stacked configuration. This parameter change allows maintaining larger, more manufacturable line widths and pad spacings while achieving high integration through vertical multiplication of functional units rather than horizontal compression.
4Quantity of substance
If advanced packaging techniques such as 2.5D and fan-out wafer level packaging are used, then integration capability improves, but the process time and cost increase
Solution Approach 1:
The patent performs preliminary packaging of individual memory chips into stacked package units before final integration with peripheral circuits. The rewiring layers are pre-formed on the encapsulating layers, and metal bumps are pre-formed on the rewiring layers, allowing parallel processing of multiple chips. This preliminary action reduces overall process time compared to sequential assembly methods.
Solution Approach 2:
The patent creates nested package units where stacked memory chips are enclosed in first package units, which are then integrated with peripheral circuit package units. This nested modular structure allows independent fabrication and testing of sub-units, enabling parallel processing and reducing total process time while maintaining high integration capability through the final assembly of pre-prepared modules.
Data Source
AI summary
A POP structure of a three-dimensional fan-out memory and a packaging method are disclosed. The POP structure includes a first package unit of three-dimensional fan-out memory device and a system-in-package (SiP) package unit of the two-dimensional fan-out peripheral circuit. The first package unit includes: memory chips laminated in a stepped configuration; first metal connection pillars connected to the memory chips; a first encapsulating layer; a first rewiring layer; and first metal bumps formed on the first rewiring layer. The SiP package unit includes: a second rewiring layer; one peripheral circuit chip; a third rewiring layer bonded to the peripheral circuit chip; second metal connection pillars; a second encapsulating layer on the peripheral circuit chip and the second metal connection pillars; and second metal bumps on the second rewiring layer. Attaching the first package unit and the SiP package unit by bonding first metal bumps to the third rewiring layer.