3D Fan-Out Packaging Structure Without TSV Stacking
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Solution Overview
Problem
Current 3D stacked bonding packaging processes for memory chips are complex, costly, and inefficient, with high material expenses, low packaging yield, and poor space utilization, leading to limited data transmission and heat dissipation issues.
Innovation Solution
A back-to-back three-dimensional stacked fan-out packaging structure that eliminates TSV stacking, using redistribution layers and vertical interconnect conductive structures to connect chips in opposite directions, reducing the need for expensive materials and processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV stacking technology is used to achieve chip interconnection, then interconnection density is improved, but process complexity and cost increase significantly
Solution Approach 1:
The patent extracts and removes the TSV stacking process from the packaging flow, replacing it with direct chip stacking and wire bonding. This eliminates the need for through-silicon via formation, copper pillar deposition, and NCF/NCP material application, thereby reducing process complexity while maintaining interconnection functionality through alternative means (wire bonding and redistribution layers).
Solution Approach 2:
The patent replaces expensive TSV-related materials (NCF, NCP, copper pillars) and equipment (TCB bonder) with more economical alternatives. Wire bonding uses conventional, cost-effective materials and equipment, while redistribution layers provide the necessary interconnection functionality at lower material and equipment costs.
2Reliability
If TCB bonding technology is used for chip stacking, then interconnection reliability is improved, but packaging yield decreases and cost increases
Solution Approach 1:
The patent replaces the TCB (thermo-compression bonding) mechanical system with wire bonding technology. Wire bonding uses a different mechanical approach that is more established, has higher yield rates, and avoids the complexity of TCB process control while achieving reliable electrical interconnection between stacked chips.
3Device complexity
If chips are stacked in a single-plane configuration, then interconnection is simplified, but space utilization and integration density deteriorate
Solution Approach 1:
The patent transitions from single-plane chip arrangement to three-dimensional stacked chip configuration with back-to-back orientation. Chips are stacked vertically with functional surfaces facing opposite directions, utilizing the vertical dimension to achieve higher integration density. Redistribution layers and wire bonding enable interconnection across multiple layers, effectively using 3D space to improve space utilization while maintaining manageable interconnection complexity.
4Reliability
If multiple TCB bonding steps are used for flip-chip mounting, then connection reliability is improved, but process time and cost increase
Solution Approach 1:
The patent extracts and removes multiple TCB bonding steps from the packaging process. By using direct chip stacking with wire bonding instead of repeated flip-chip mounting, the process time is significantly reduced while connection reliability is maintained through the established wire bonding technology and proper chip stacking design.
Data Source
AI summary
Disclosed is a back-to-back three-dimensional stacked fan-out packaging structure and a preparation method thereof, and also a packaging module utilizing the packaging structure and a preparation method thereof. The solution provided by the present invention does not require chip TSV stacking, and the stacked chips may be electrically connected in the shortest vertical interconnection manner, thereby ensuring a high interconnection density and transmission performance while reducing packaging costs and improving packaging yield.